[SI-LIST] Re: DC/DC converter output dip
- From: Mike Brown <bmgman@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 06 Aug 2003 19:49:37 -0500
I think Gary has hit on the problem: There's a power oscillator in the
circuit! I suspect that it may be the absense of a soft-start circuit
on the FET's input. Here's the hypothesized cycle: 3.3 comes up with
the FET off; the other supplies come up, the FET turns on quickly,
slamming a discharged 3.3 volt load cap across the 3.3 supply, which
then shuts down. In turn the other supplies shut down and the FET turns
off, then the 3.3 comes up. Ad infinitum.
There may be some other mechanism involved, but this one could do it.
For this to happen, there must be a large cap on the load side of the
FET - probably a lot larger tyhan the regulator's output C.
Addition of a rate limiting circuit to the FET gate will limit the
turn-on transient current.
Note that the FET must be large enough to handle the energy of the
charge cycle; it will be in the linear region for some relatively long time.
HTH!
Mike
Pratt, Gary wrote:
>Jean-Pierre,
>How is the common 1.2 reference voltage generated? And, what supply is
>used for the op-amps? From your first description it sounded like a
>control loop problem (Veneble being an excellent suggesting for solving
>that type of problem). But, now, it sounds like you may have a
>relaxation loop related to the switching of the MOS transistor and its
>affect on the 3.3 supply.
>
>Can you provide a JPEG of the schematic containing the supplies,
>op-amps, MOS transistors and associated circuitry?
>
>Gary
>
>
>
>-----Original Message-----
>From: Jean_Pierre.Bouthemy@xxxxxxxxxx
>[ mailto:Jean_Pierre.Bouthemy@xxxxxxxxxx
><mailto:Jean_Pierre.Bouthemy@xxxxxxxxxx> ]
>Sent: Wednesday, August 06, 2003 12:21 PM
>To: si-list@xxxxxxxxxxxxx
>Cc: Tom.Currelly@xxxxxxxxxxx
>Subject: [SI-LIST] Re: DC/DC converter output dip
>
>
>
>Hi Chris,
>
>The design is a little bit complex. Let me try to clarify.
>A +5V isolated converter is used as a "housekeeping" voltage that comes
>first in order to supply the monitoring circuits.
>I have a 3.3V isolated DC converter whose output feeds 3 non-isolated DC
>
>converters: 2.5V, 1.8V and 1.5V.
>The 4 voltages 3.3V, 2.5V, 1.8V and 1.5V are all monitored with the same
>
>way. They each feed an op-amp with a resistor divider on the input+. The
>
>input- is a common reference voltage of 1.2V. The feedback is made with
>a
>1Mohm resistor between input+ and the output.
>The output of the op-amp are pulled-up together to the "housekeeping"
>+5V
>and feed a circuit to drive the MOS transistors at the output of the DC
>converters.
>When all four voltage have correct levels, the common outputs are at
>high
>level, and a signal is activated to open the MOS so that the devices on
>the
>board can be supplied.
>Hope you better understand my design.
>
>The noise I have on the +2.5V output is not like ripple. The signal is
>high
>at 2.5V during 90ms and then a 2ms pulse down to 1.5V.
>I have investigated and it seems like it is due to the 90ms ripple noise
>on
>the +5V output. But the problem is still nearly the same: when I remove
>the
>resistor of the the +5V monitoring circuit, I have no noise anymore.
>Strange isn't it?
>
>Could a simple RC filter at the output of the +5V DC converter do the
>job
>of phase margin compensation?
>Any help will be welcome.
>
>Jean-Pierre
>
>
>--------------------------------------------------------------------
>Jean-Pierre BOUTHEMY
>Hardware Design Engineer
>ALCATEL - Mobile Networking Division (MCG)
>Mobile Core R&D
>+33 (0)2 99 26 08 18
>mailto:jean_pierre.bouthemy@xxxxxxxxxx
><mailto:jean_pierre.bouthemy@xxxxxxxxxx>
>--------------------------------------------------------------------
>
>
>|---------+------------------------------>
>| | Christopher |
>| | Jakubiec |
>| | <Christopher.Jakubi|
>| | ec@xxxxxxx> |
>| | Sent by: |
>| | si-list-bounce@free|
>| | lists.org |
>| | |
>| | |
>| | 06/08/2003 17:52 |
>| | Please respond to |
>| | si-list |
>| | |
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> | Subject: [SI-LIST] Re: DC/DC converter output dip
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>
>
>
>Jean-Pierre,
>
>As I understand from your description you have a 2.5V output from the
>dc-dc
>
>converter that feeds into an op-amp comparator by using a resistor
>divider
>on
>the + and - inputs to the op-amp. Is this correct? It sounds like a
>very
>basic
>comparator setup. Are you using negative feedback with nothing
>connected
>inbetween the output and input of the op-amp?
>
>Chris Jakubiec
>Sun Microsystems
>
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