[SI-LIST] Chip capacitance effect for SSN simulation
- From: Cristian Gozzi <cristian.gozzi@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sun, 16 Oct 2011 11:25:27 +0200
Hi SI members
I'm simulating DDR2 SSN for a Probe Card system
for those that are not familiar with this application, Probe Card is an
hardware application to physical connect DIE pads/bumps at wafer level to
ATE system during Electric Wafer Sort
In my case Probe-Card is build by a vertical needles that touch DIE pads +
PCB
During frequency domain analysis of my system, I got a strong PDN peak
impedance around 1GHz
This peak impedance was due to anti-resonance effect between PCB PDN system
and needle PWR parasitic effect
so during time domain analysis I got a strong and unreasonable AC noises
also with only 2 switching DQ
In my spice deck I only used IBIS model provided by silicon vendor and I
excluded RLC package effects, since my application is contacting directly
wafer.
I think I should include chip power rail capacitance effect in order to
filter high freq noises.
But my question is: which C and R value should I use?
Is these value included in IBIS model?
NOTE: consider that I had to reduce number of PWR needles used for HFSS
simulation, so I only selected those needles around my 8 DQ + 2 DQS
So I think I should put a lower value of chip capacitance than total one
Any comments from expert are more than welcome
Thanks in advance
Regards
Cris
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
