[SI-LIST] Re: Buried Capacitance thread comments (The whole t hing)
- From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 6 Dec 2001 14:53:35 -0800
Trick question, you are trying to pin a package noise issue to a PCB
solution.
The fact that there is an SSO problem on the package means you should solve
it at the package level. Power/ground distribution has been choked between
the package and PCB as such there is nothing you can do on the PCB power
distribution to eliminate the noise. The noise will come out through the
signals as ringing due to the SSO noise on high or low signals. I don't
think you can decouple a signal out of noise. The more reason to cage the
signal trace between i/o power and ground planes as striplines and stitch
the pcb with both power and ground vias to form a faraday cage. Nothing you
can do with Zycon planes.
[MLC] For signal excitation, we are in absolute agreement. However, if the
planar noise is caused by SSO effects on the chip power/ground interface(s),
board resonances will be excited. Then, the BC approach is your (next?) best
friend because of its basic low impedance and lossy characteristic at higher
frequencies.
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