[SI-LIST] Re: Buried Capacitance thread comments (The whole t hing)
- From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 3 Dec 2001 15:36:41 -0800
Larry,
Glad you point out the power impedance distribution issue.
I always have this simplistic view of power distribution
as those Japanese garden water irrigation that starts with
a water tap, fill the first bucket up, when its full it
flips and fill the next one, repeated until the last
bucket water the plant. As such you can do similar analysis
on power distribution of highspeed IC. Starting with the
appropriate on die switching activities you can progressively
simulate the effect of decoupling all the way to the power
pod that supply the IC. In my opinion, the optimal design
will be starting with the closest decoupling cap (most
likely on die) observe the current in and out of the caps
(if the current is +ve, the cap is helping out the decoupling
if the current is -ve, the cap is starting to deplete and
need a bigger bulkier capacitor upstream towards the power
supply) I consider this methodology as the economics of
decoupling, used the minimal amount of decoupling to get
the job done with the least cost. There is however one
more complication. Unlike the garden analogy, the way the
bucket (caps) get filled and discharged is heavily dependent
on the type of caps and it also depends on their location,
the way charge flow between the buckets. Based on most of
the analysis I've done, the appropriate cut off point between
the package and the PCB happens between 100-200MHz. Of course
this is not a fixed rule, if the buckets downstream (towards the
die) is inappropriately size, you need more buckets (caps) and
better flow paths (between the caps). I think a better solution
to fix the problem should come from fixing the downstream caps
and as package designers, it is important for them to understand
(in a case by case bases) what is the die and package interaction
on decoupling issues. What you have suggested seems to be fixing
the flow path upstream at the PCB, while I believe my opinion is
doing the same upstream (on die and on package). Its the economics
of decoupling. Both will work but at a cost. Is it more expensive
to lower the impedance path on a smaller package with less caps or
is it more expensive to pay for the 2 mil core planes and more
caps on the PCB ?
As for the claim that <2 mil core can eliminate large amount of
bulk caps. One has to consider whether the ESL,pad and via inductance
of the decoupling caps dominates the impedance path or the much
lower mutual plane inductance has a more profound effect. I could
be wrong but I believe the former is more pronounced.
-----Original Message-----
From: Larry Smith [mailto:ldsmith@xxxxxxxxxxxxxxxxxx]
Sent: Monday, December 03, 2001 11:03 AM
To: si-list@xxxxxxxxxxxxx
Cc: michael.freda@xxxxxxxxxxx
Subject: [SI-LIST] Re: Buried Capacitance thread comments (The whole t
hing)
One thing is for sure: Whenever mud is thrown, everyone gets muddy.
Let's see if we can keep our comments on a technical level. Everyone
is entitled to an opinion. The last opinion left on the table does not
necessarily become physical law.
GHz noise definitely appears on the PCB core power and ground planes.
It is a function of frequency. It's magnitude closely follows the
impedance profile associated with plane resonances. Take your spectrum
analyzer and measure it as you sweep the clock frequency it you don't
believe that. This noise will probably not cause SI problems but may
cause EMI problems depending on a lot of other factors. Thin power
plane dielectrics definitely reduce the noise.
Some one has said that there can be no noise above 200 MHz on the PCB.
It is true that the inductance of the package attenuates the noise from
the silicon. The chip capacitance and package inductance form a nice
low pass filter. But how much attenuation does that filter have? If
it has 40 dB, that is only a factor of 100. We may have 100 watts of
power at 1 GHz on the chip and 1% escapes. But, 1 watt of power at
1GHz loose on our PC boards is a major issue! Several papers have been
written by authors at Sun and Georgia Tech that give both theoretical,
simulated and measured results for thin laminates. There is no
question that they may be used to dampen a noise problem if it exits.
(In this case, problem is defined as "can't ship the product.")
Buried capacitance is not really the issue. A much more important
property of thin laminates is the spreading inductance: the thinner the
laminate, the lower the inductance. This is the inductance that stands
between the the uP chip and nearly all of the decoupling capacitors
everywhere on the PCB. While it is possible to place decaps directly
under the uP package, most of the decoupled power will flow to the
processor through the inductance of the power planes. The thinner, the
better.
The real issue is impedance. The chip circuits want to look out to the
outside world and see a low impedance (target impedance, which is
easily calculated). The power planes have impedance that is directly
proportional to the thickness of the dielectric between Vdd and Gnd.
The power plane impedance is in series with most all of the energy
reservoirs including faraway plane capacitance, discrete capacitors
and the VRM. If the power planes are not low impedance, the chip is
not going to look out and see low impedance from the PCB.
Somebody seems to have a patent on buried PCB capacitance, as silly as
that may seem. Why don't we just declare that impedance and inductance
are the important parameters for power planes? Let's make this public
domain so that nobody gets a patent on it. We can do that right now on
this list... :) Power distribution, clean signal environments and EMI
performance benefit greatly from the low impedance, low inductance and
high damping properties of thin laminates. The buried capacitance
between the planes is just an incidental benefit. We use thin
laminates as a conduit to pipe in power, not necessarily to replace
discrete capacitors.
Istvan Novak is hosting a technical session on thin laminates at Design
Con this year. I hope that it is well attended.
regards,
Larry Smith
Sun Microsystems
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
