[SI-LIST] Re: Antennas (contd)
- From: "Kevin Skey" <Kevin.Skey@xxxxxxxxxxxx>
- To: <gs_si91@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 12 Sep 2003 11:24:47 -0400
Hi Gaurav,
The Antennas you are referring, like you said, to have to do with effects
during the manufacturing process. The high-level answer is...since many of
the fab chemicals and materials are ionized, charge can tend to accumulate
on long flat surfaces (surface area dependent) during manufacturing, such as
your routing wires. Since your wires are connected to the gates of MOSFETs,
the charge can build up to a level that will cause oxide damage. This gets
worst as you shrink feature size.
The fab has a set of DRC rules to help routing and DRC Fixing tools avoid
and detect these potential problems. There are a couple of ways today's
routing tools perform prevention. One way is to avoid long wires on a single
metal layer by performing stitching. This is where you break up the route by
changing to a different metal layer if you pass a length rule. i.e. toggling
between m4 and m5 for a given route. Another is the insertion of reverse
bias diodes to the long routes to drain away any charge.
An EDA vendor should be able to tell you how they perform these steps in
their specific tool flow.
Hope this was helpful.
Regards, Kevin
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of G S
Sent: Wednesday, September 10, 2003 12:05 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Antennas (contd)
Hi all,
Firstly, I'd like to thank the people who provided some time and insight
into Antennas and their effects. I appreciate it.
I was hoping to get some more information on what are antennas and their
effects that we see in the backend IC Design (Physical Design), in contrast
to the wireless antennas. I apologize for being unclear in my previous
email.
Antennas are some effects that could occur during the manufacturing stage of
IC design and wanted to know more about these and their causes, and how
would one rectify these after place-n-route of the chip.
I would appreciate any kind of insight on this as this would be beneficial
to me.
Thanks again.
Regards,
Gaurav.
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