[SI-LIST] Re: Antennas (contd)
- From: "Frank Dunlap" <fdunlap@xxxxxxxxxxxxxxxxx>
- To: <gs_si91@xxxxxxxxx>
- Date: Mon, 22 Sep 2003 16:57:34 -0700
Hi Gaurav,
I didn't see a response to your question, so here's one:
The antennas that I think that you are talking about are sections of
interconnect that ultimately connect to the gate of a MOS transistor.
During manufacturing, the patterning of these interconnect sections by
plasma etching, leads to a potential build-up of charge. If too much
charge builds up, the fragile gate oxide of the MOS transistor may
become damaged. The effect is also referred to as "plasma induced gate
oxide damage."
Manufacturing design rules limit the amount of interconnect that can be
directly attached to a gate, as the total area and perimeter of the
interconnect are factors in how much charge builds up. It's common
practice to connect small diodes to sections of interconnect to provide
a discharge path for charge generated during the manufacturing process.
With such diodes, larger sections of interconnect can be attached to a
MOS transistor's gate.
Regards,
Frank=20
-----Original Message-----
From: G S [mailto:gs_si91@xxxxxxxxx]=20
Sent: Wednesday, September 10, 2003 9:05 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Antennas (contd)
Hi all,=20
Firstly, I'd like to thank the people who provided some time and insight
into Antennas and their effects. I appreciate it.=20
I was hoping to get some more information on what are antennas and their
effects that we see in the backend IC Design (Physical Design), in
contrast to the wireless antennas. I apologize for being unclear in my
previous email.=20
Antennas are some effects that could occur during the manufacturing
stage of IC design and wanted to know more about these and their causes,
and how would one rectify these after place-n-route of the chip.=20
I would appreciate any kind of insight on this as this would be
beneficial to me.=20
Thanks again.
Regards,
Gaurav.=20
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