Krishna,
There are two factors which effect which threshold to assume. First is that
the AC and DC thresholds can change
depending on speed bin. At higher speed bins the threshold tend to get
tighter. The tighter thresholds help
enable the higher speeds. Then within each speed bin you have a standard AC
threshold and a reduced
AC threshold, which evokes a setup penalty. The lower threshold can produce
better margins, despite the penalty,
in heavy loading cases where slew rate is very slow and/or eye height is small.
As far as derating at slew rates above 2V/ns, technically the derating
continues the increase above 2V/ns, based on
the original derating theory, but some empirical data suggests you can freeze
derating at the value shown for 2V/ns
with minimal risk.
Brian Moran
Intel Corporation
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Arjun Krishna
Sent: Wednesday, April 15, 2015 9:12 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Ac threshold timings
Hi Experts
Here's my question.
In ddr3 simulation I have come across AC175, AC150 & AC135.
I have confused, How these threshold can be chosen how the designers consider
these spec. and when to apply. Is there any standard specified.
How the derating values are are considered, Means my slew rate measurement is
4.9v/ns sec but the max specified is 2v/ns. Which value I should as the base
value.
I'm. awaiting for your replies
Krishna.
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