Hi Arjun -
I think you and Mo Han are asking very similar questions.
I think you first need to read JDEC and your memory datasheets to understand
how to measure the slew rate. The slew rate measurements are not the 20%-80%
like I usually see in ASIC timing. JDEC measures between specific levels, and
Setup is measured a little differently than Hold.
I can't measure the waves by hand accurately, so I post-process my simulation
data.
Second, if you are lucky, then your slew rates will be on the derating charts,
then you just add the derating to your setup and hold measurements. (My
results are usually off the charts, and so I must understand how the charts are
made)
Paul Callahan
On Semiconductor
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Arjun Krishna
Sent: Wednesday, April 15, 2015 11:12 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Ac threshold timings
Hi Experts
Here's my question.
In ddr3 simulation I have come across AC175, AC150 & AC135.
I have confused, How these threshold can be chosen how the designers
consider these spec. and when to apply. Is there any standard specified.
How the derating values are are considered,
Means my slew rate measurement is 4.9v/ns sec but the max specified is
2v/ns. Which value I should as the base value.
I'm. awaiting for your replies
Krishna.
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