[SI-LIST] AW: Re: AW: Re: optimize Equalization and De-emphasis settings
- From: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 25 Nov 2010 09:34:01 +0100
Hi Scott,
many thanks for the detailed clarification. This was exactly the answer I was
looking for, even though I was hoping there is an easier way. I tested impulse
response and frequency sweep simulation for the models, but didn get a response
at all. I also tested step response which somehow worked, but the output didn't
make much sense. I think the models aren't throughly linear, even though the
input and output stages seem to be.
Based on that I will go ahead with "trial and error" settings sweep to find the
optimum.
I'd like to thank everyone who responded online and offline for their effort
and support.
BR
Gert
http://www.mesago.de/de/SPS/home.htm
Besuchen sie uns auf der SPS/IPC/Drives in Nürnberg, vom 23. - 25. November
2010, in Halle 10, Stand 130.
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-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Scott McMorrow
Gesendet: Mittwoch, 24. November 2010 23:14
An: si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] Re: AW: Re: optimize Equalization and De-emphasis settings
Guys,
With all due respect, the problem Gert has is one of non-Linear, non-LTI
optimization. The optimal equalization for one stage in these multiple link
systems is not optimal for multiple stages cascaded, especially when distorted
waveforms are passed through non-linear switch matrices.
Given the channel that you have Gert
(driver-PCB-switch-PCB-switch-PCB-reclocker-PCB-Receiver)
You can treat this as two problems that can be optimized separately.
1- (driver-PCB-switch-PCB-switch-PCB-reclockerInput)
2 - (reclockerOutput-PCB-Receiver)
#2 is amenable to the approaches that multiple people have suggested.
#1 is a PITA. If the switches operate in the linear amplification region, then
this is just a cascaded amplifier/equalizer problem, not unlike a video cable
system. You have to keep the signal in the linear region at all inputs, above
the noise floor of the input amplifier, and below the clipping region. In that
case, each switch and interconnect can be handled as a transfer function,
modeled as s-parameters, and optimized accordingly. But ... you need to know
what they are.
If any of the amplifiers clip then you have the impact of clipping on the
spectrum, which then causes the transfer function to be dependent on the
received signal waveform. If the clipping is reasonably predictable, then you
still might be able to use linear assumptions.
If limiting amplifiers are used in the silicon, then you have a really nasty
non-linear problem, since a limiting amplifier looks like a digital sampler
with amplitude as the trigger, but with finite gain. The transfer response
changes with time.
If I were attempting to optimize this (and thankfully I'm not!) I would try to
characterize the switch that you're using, and determine just how linear it is
from input to output with whatever the nominal equalization is. If the switch
is fully composed of linear amplifiers, and no switch elements, then you can
perform frequency domain sweeps from input to output, with the input biased to
the correct common mode voltage, and a variable differential p-p voltage across
multiple sweeps. This will give you a series of curves that describe the
transfer function as a function of input amplitude. With some luck, you'll find
a linear sweet spot that is large enough to allow for latitude in optimization.
If the model is not amenable to FD sweeps, then just perform impulse response
simulations at various amplitudes and derive the transfer response.
If there is limiting or clipping going on, then you might be able to
characterize the silicon at an amplitude low enough to stay out of the
clipping/limiting region that is linear, and then model the limiting amplifier
behaviorally.
Once you find a characterization method that "works" then use the p-p voltage
in the center of the linear range to characterize each equalizer setting in the
switch. From these, you can derive a simplified model for each equalizer boost
setting.
Good luck
Scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of Teraspeed Consulting Group LLC
On 11/24/2010 3:39 AM, Havermann, Gert wrote:
> Hello Vladimir,
>
> thanks for the clarification (especially about StatEye). As you say, there is
> no digital processing involved, thus StatEye will not be much help.
>
> The logical step to simulate each passive link separately doesn't apply
> either. I started that way, but the silicon passes a lot of effects thru to
> the output (they behave more like an amplifier than a switch).
>
> You are right, that if a bit doesn't pass one of the switches it is lost for
> good, but a bit with decreased amplitude or timing will influence the next
> channel section. In my case, I can for instance use one silicons equalizer to
> get a better signal output at the next silicon. The timing portion of the
> "over"- equalization passes thru the silicon and acts like a pre-equalization
> (is just a small effect, but given the fact that the passive links are 45"
> long and contain multiple vias ith long stubs (>200 mil via stub!!) I need
> all the performance I can get.
>
> BR
> Gert
>
>
> http://www.mesago.de/de/SPS/home.htm
>
> Besuchen sie uns auf der SPS/IPC/Drives in Nürnberg, vom 23. - 25. November
> 2010, in Halle 10, Stand 130.
>
> ----------------------------------------------------------------------
> ---- Absender ist HARTING Electronics GmbH& Co. KG; Sitz der
> Gesellschaft: Espelkamp; Registergericht: Bad Oeynhausen;
> Register-Nr.: HRA 5596; persönlich haftende Gesellschafterin: HARTING
> Electronics Management GmbH; Sitz der Komplementär-GmbH: Espelkamp;
> Registergericht der Komplementär-GmbH: Bad Oeynhausen; Register-Nr.
> der Komplementär-GmbH: HRB 8808; Geschäftsführer: Edgar-Peter Duening,
> Torsten Ratzmann -----Ursprüngliche Nachricht-----
>
>
> Von: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] Im Auftrag von Dmitriev-Zdorov,
> Vladimir
> Gesendet: Dienstag, 23. November 2010 23:46
> An: si-list@xxxxxxxxxxxxx
> Betreff: [SI-LIST] Re: optimize Equalization and De-emphasis settings
>
> Hi Steve,
>
> As was stated in the original question: "I'm looking for some technique or
> algorithm to determine the desired amount of equalization just by examining
> each silicon's input signal". Therefore I think that the purpose was to find
> equalization in every analog portion separately. Digital processing in the
> silicon itself is not involved.
>
> We cannot generate the combined 4-port model that includes switches and
> channels, or equally we shouldn't produce combined model for the channels
> separated by switches. Switch is not something that can contribute to the
> transfer function or S-parameters, because it is a heavily non-linear
> transformation - similar to A/D converter.
>
> Logically, it also does not make sense to combine links because if the first
> switch fails (produces incorrect bit) all others should fail too, and no
> equalization in the subsequent links will help. Therefore equalization should
> be constructed separately for each analog link.
>
> In Hyperlynx FastEye, there is a possibility to find optimal set of FFE and
> DFE taps, given the channel schematic, S-parameters or its equivalent step or
> pulse response.
>
> Vladimir
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Stephen Zinck
> Sent: Tuesday, November 23, 2010 6:28 AM
> To: 'Havermann, Gert'; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: optimize Equalization and De-emphasis settings
>
> Hi Gert,
>
> If you are using Altera or Broadcom, they have applications that automate
> this process (other vendors may also have this capability). All you do is
> provide a 4-port S-parameter model of your system and the tool will tell you
> the required settings for the most open eye. Pretty cool.
>
> I use SIWave from Ansoft to extract all the features for a particular link
> (BGA pads, traces, accurate via models, passive pads, etc.). The output of
> this tool is 4-port S-parameters. If multiple system S-parameter files are
> required for each element (switch-backplane-switch), these models are then
> concatenated in Ansoft's Designer SI. This tool can accurately concatenate
> S-parameter files into a single file for the entire system.
>
> Best regards,
> Steve
>
> Stephen P. Zinck
> High-Speed Signal Integrity Consulting Interconnect Engineering Inc.
> P.O. Box 577
> South Berwick, ME 03908
> Phone - (207) 384-8280
> Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
> Web - www.interconnectengineering.com
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Havermann, Gert
> Sent: Tuesday, November 23, 2010 07:05 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] optimize Equalization and De-emphasis settings
>
> Dear Experts,
>
> is there any way to determin the optimum settings for Equalization and
> De-emphasis in a channel simulation?
>
> Situation: I'm running simulations of cascaded channels
> (driver-PCB-switch-PCB-switch-PCB-reclocker-PCB-Receiver). Each silicon has
> analog equalization and de-emphasis, only some have ECR, thus i can't just
> simulate section by section.
>
> Simulation takes very long, thus I would like to start with optimum settings.
> I'm looking for some technique or algorithm to determin the desired amount
> of equalization just by examining each silicon's input signal (Eye, spectrum,
> timing...).
>
> Any thoughts or paper reference is appreciated.
>
> BR
> Gert
>
> http://www.mesago.de/de/SPS/home.htm
>
> Besuchen sie uns auf der SPS/IPC/Drives in Nürnberg, vom 23. - 25. November
> 2010, in Halle 10, Stand 130.
>
>
> ----------------------------------------------------------------------
> ---- Absender ist HARTING Electronics GmbH& Co. KG; Sitz der
> Gesellschaft: Espelkamp; Registergericht: Bad Oeynhausen;
> Register-Nr.: HRA 5596; persönlich haftende Gesellschafterin: HARTING
> Electronics Management GmbH; Sitz der Komplementär-GmbH: Espelkamp;
> Registergericht der Komplementär-GmbH: Bad Oeynhausen; Register-Nr.
> der Komplementär-GmbH: HRB 8808; Geschäftsführer: Edgar-Peter Duening,
> Torsten Ratzmann
>
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