[SI-LIST] Re: AC series capacitor position in high speed differential signals

  • From: "Powell, Jon N" <jon.n.powell@xxxxxxxxx>
  • To: Istvan Novak <istvan.novak@xxxxxxx>, Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
  • Date: Thu, 13 May 2010 08:33:02 -0700

I think the bigger issue on PCIE is that selection of cap placement forces a 
strategy for layer selection, via placement, number of vias, and stub length. 
For instance, if you are routing on a Stripline layer, placement of the cap 
near the connector (on the bottom) can save you a via and stub.

Jon Powell

Disclaimer:
The content of this message is my personal opinion only and although I am an 
employee of Intel, the statements I make here in no way represent Intel's 
position on the issue, nor am I authorized to speak on behalf of Intel on this 
matter.
EPSD Product SI

將


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Istvan Novak
Sent: Wednesday, May 12, 2010 8:55 PM
To: Lee Ritchey
Cc: fei xue; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: AC series capacitor position in high speed differential 
signals

Lee,

As it was pointed out in earlier threads, location does make a 
difference unless reflections are
negligibly small.  Assuming linearity, when we move components around, 
reciprocity prevails,
but voltage transfer function from source to load will change, which in 
turn impacts eye
parameters.

Regards,

Istvan Novak
Oracle-America


Lee Ritchey wrote:
> This has been answered before on this forum.  Since the circuits are
> linear, it does not matter from a signal integrity point of view.
>
> Lee
>
>
>   
>> [Original Message]
>> From: fei xue <harrison_cls@xxxxxxxxxxxx>
>> To: <si-list@xxxxxxxxxxxxx>
>> Date: 5/12/2010 11:35:49 AM
>> Subject: [SI-LIST] AC series capacitor position in high speed
>>     
> differential signals
>   
>> Hello all,
>> We often can get different guideline of placing capacitor position when
>>     
> placing AC series capacitor on high speed differential signals, like PCIe,
> SAS or LVDS signals. sometimes we followed the guideline to put capacitors
> near driver, sometimes near multi-connection connectors or sometimes put it
> near receivers.
>   
>> Could anybody tell me what is the consideration of capacitor placing
>>     
> position? Thanks!
>   
>> Harrison
>>
>>
>>       
>>     

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
                //www.freelists.org/archives/si-list
 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
                //www.freelists.org/archives/si-list
 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

Other related posts: