[SI-LIST] Re: AC Coupling bandwidth Consideration for 8b/10b
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Curt McNamara <curt.mcnamara@xxxxxxxxxxx>
- Date: Thu, 14 May 2009 16:13:03 -0700
ESR is roughly 1/C^0.4. This varies by package with the power getting
smaller for smaller packages.
Steve
Curt McNamara wrote:
> Is this comment true for all types of dielectric?
>
> In other words: does ESR decrease with increasing capacitance even if
> dielectric changes?
>
> Often the highest values of capacitance have the worst dielectric
> characteristics.
>
> Curt
>
>
> Curt McNamara, P.E. // principal electrical engineer
> Logic Product Development
> 411 Washington Ave. N. Suite 400
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> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of Scott McMorrow
> Sent: Thursday, May 14, 2009 12:57 PM
> To: wolfgang.maichen@xxxxxxxxxxxx
> Cc: Mike Harwood; si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: AC Coupling bandwidth Consideration for 8b/10b
>
> I have to disagree slightly with you Wolfgang. You are correct if you
> are talking about different capacitor body styles. However, as long as
> the capacitor is housed in exactly the same package style (i.e. 0603,
> 0402, 0201), the largest capacitance in a particular package from a
> manufacturer always has the lowest series resistance and inductance.
> There is a balancing act that needs to take place above 10 Gbps. At low
> frequencies we are concerned with charging time constants, however, to
> faithfully pass the waveform edges through a capacitor it is necessary
> to design a minimum return loss transition. This depends heavily on the
> location of the lowest plate in the capacitor. That location can vary
> as much as 10 mils in the z-axis, which is significant when passing
> energy at 20-40 GHz.
>
>
--
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