[SI-LIST] A Thermal Relief Question
- From: Ned.Dempsher@xxxxxxxxxx
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 16 Sep 2010 11:15:36 -0400
Hi SI-LIST,
I have three rather specific questions regarding the use of thermal
reliefs and could not find anything in the archives on this.
This is a through-hole power supply pin carrying 20 amps.
We are being directed to limit the number of ground breakout layers,
which contain thermal reliefs, to just a couple of layers to meet
solderability requirements.
At the same time we are being directed to, in some cases, add additional
current paths to the planes using extra vias because the thermal relief
traces will experience excessive current based on IPC2221 trace
temperature rise calculations.
I am on-board and understand how the solderability requirements drive
the breakout but have concerns about the limitations being imposed by
the temperature rise calculations.
IPC2221 based calculations in our case are being applied to thermal
reliefs which are very short traces heat sunk to a large plane while the
IPC data was collected on long traces with no special heatsinks.
First, do you agree that IPC2221 is not a good way to go in determining
the amount of current that is allowed to traverse a thermal relief?
Second, short of a thermal analysis tool; is there any other way or data
to provide some guidelines as to how much current is allowed to travel
through power supply thermal reliefs? (Voltage drop across the thermal
reliefs is acceptable.)
Third, can anyone see anything wrong with doing this from a PI/SI
perspective?
I know there will be a millivolt or two extra drop due to the reduction
in the number of ground planes feeding the supply but all of the ground
planes are tied together with hundreds of vias at the load so that I
believe there should not be any higher frequency SI or PI effects due to
this small change at the supply??
Thanks for Listening,
Ned Dempsher
L-3 Communications
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