[SI-LIST] Re: 6 Layer Stack-up
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "Vishram Pandit" <vishrampandit@xxxxxxxxxxx>, larry.smith@xxxxxxx
- Date: Fri, 12 Sep 2003 12:58:43 -0700
Vishram,
Six layers is a tough stackup to use. If you make signals happy, you don't
have much of a planecapacitor. If you make the plane capacitor happy, you
don't have good SI. I use your first stackup and flood the unused space in
the signa layers with copper. This I attach to the appropriate power rail
and get enough plane capacitor to make many of these designs happy.
Failing that, you need two more planes.
Lee
> [Original Message]
> From: Vishram Pandit <vishrampandit@xxxxxxxxxxx>
> To: <larry.smith@xxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>
> Date: 9/10/2003 11:14:51 AM
> Subject: [SI-LIST] 6 Layer Stack-up
>
>
>
>
>
>
> We have been using the stackup S-G-S-S-P-S.(stack up no. 1). Now, with
> suggestion from SI-List, on newer high speed designs, I would like to use
G
> adjacent to P with 4-6 mils of separation. It will give me very good
> decoupling. However, I have only 6 layers so I have to have my stack-up as
> S-S-G-P-S-S (stack up no. 2). Will it be okay?
>
> Here are pros and cons as per my analysis:
>
> 1] Stack up no. 1 gives you poor P/G decoupling, wheras stack up no. 2
gives
> you very good P/G decoupling.
>
> 2] P/G Decoupling caps at higher frequencies (>500MHz) are not required
for
> stack up no. 2
>
> 3]Stack up no. 1 will shield the EMI radiation from internal traces
because
> of G(Layer 2) and P(Layer 5).we will loose this benefit for the stack up
no.
> 2.
>
> 4] For stack up no. 1, signals on Layer 1, 3, 4, and 6 had a reference
> plane.For stack up no. 2, only signals on Layer 2 and 5 have reference
> planes. So I have to be careful routing high speed signals on Layer 1 and
> Layer 6.
>
> Has anyone implemented stack up no. 2 on 6 layer board? Which stack up is
> advisible for 6 layer board? What are pros and cons for stack up no. 1
and 2
> for a 6 layer board?
>
>
> Thanks,
>
> Vishram
> >From: Larry Smith >Reply-To: larry.smith@xxxxxxx >To:
> vishrampandit@xxxxxxxxxxx >CC: si-list@xxxxxxxxxxxxx,
> Charles.Grasso@xxxxxxxxxxxx >Subject: [SI-LIST] Re: Power Integrity (was:
> UltraCAD ESR and Bypass Capacitor Caculator) >Date: Mon, 18 Aug 2003
> 09:11:42-0700 >>Vishram - I agree. My general approach is to address the
PI
> problem first >and make sure that the silicon circuits have clean power.
> Thisinvolves >management of capacitance and inductance at the PCB, package
> and chip levels. >Next, address the SI problems by making sure that all
high
> speed signals have >a good return current path. After doing these two
> things,many EMI problems >will be eliminated. >>I have also been able to
fix
> EMI problems at multiple 100's of MHz by >using decoupling capacitors. But
> the higher the frequency gets, the >harder it is to do this. Capacitors at
> this frequency usually will not affect >the quality of the power as
measured
> at the silicon circuit terminals (PI), >but they might effect emmissions.
> >>After we began using thin power plane >dielectrics, I don't believe we
> havefound any EMI problems that can >be fixed with discrete decoupling
> capacitors. But if your product does >not have thin power plane
dielectrics
> (4 mil or less) for cost or >other reasons, EMI problems can _sometimes_
be
> fixed with caps. If >this works, it is usually not a very robust solution.
> Ifsome little >thing changes, the EMI problem often crops back up again.
> >>regards, >Larry Smith >Sun Microsystems >>Vishram Pandit wrote:
> >>>>>>Larry, >>>>Very nice explanation. PI influences SSN, and SSN
> influencesEMI. EMI is >>influenced by PI and SI. If we have sound PI and
> also, reduce the SSN, then >>EMI (due to that aspect of the circuit) is
> mitigated. Would you agree? >>>>As mentioned in my pevious mails, I have
> seenimprovements in EMI at higher >>frequencies (as high as 800MHz) with
> decoupling capacitors, and changing the >>P/G structure to improve the
> impedance. Your email states that PI is >>characterized by P/G impedance
and
> decaps for PI are effective up to 100MHz. >>However, in my case, I reduced
> the 800MHz impedance further by decaps >>betweenP/G, and by improving the
> P/Gstrucutre, and it helped improve the >>EMI. Thus, improving PI at
800MHz
> improved the EMI.Apart from chaning the >>structure of P/G, decaps (value,
> ESL, locations) played important part in >>it. >>>>I will appreciate your
> comments. >>>>Thanks, >>>>Vishram Pandit >>>>Senior Member Techincal Staff
> >>>>Hughes Network Systems >>>>>From: Larry Smith >Reply-To:
> Larry.Smith@xxxxxxx >To: >>si-list@xxxxxxxxxxxxx,
> Charles.Grasso@xxxxxxxxxxxx>Subject: [SI-LIST] Power >>Integrity (was:
> UltraCAD ESR and Bypass Capacitor Caculator) >Date: Fri, 15 >>Aug 2003
> 14:04:39 -0700 (PDT) >>I changed the thread name to better reflect >>the
> subject.. >>Some of us at Sun have begun using a different word for the
> >>power >distribution problem, "power integrity." This phrase helps to
> >>>distinguish three major topics: power integrity (PI), signal integrity
> >>>(SI)and EMI. Power integrity is the issue that Charles is addressing
>and
> >>signal integrity is what Kim is addressing in his very nice web
>posting.
> A>>lot of the confusion could be eliminated by using clearer >terminology.
> >>I>>think of the "power integrity" problem as having only two nodes: Vdd
> >and >>Gnd. There are no signals involved. For the power integrity
>problem,
> we are >>concerned with delivering many watts of power, often at >low
> voltageand >>highcurrent, to modern digital technology. The big >issues
are
> transient >>current and DC loss. A good example is an >advanced micro
> processor that >>draws as much as 100 watts of power at 1 >volt (100
amps).
> The processor can >>go from an idle state to a fully >active state in
just a
> few clock cycles (1 >>nSec). The silicon circuits >may consume 50 amps and
> then 100 amps just a >>fewcycles later. >Delivery of this 50 watt
transient
> through the various >>timeconstants, >which range from nSec to mSec (chip,
> package, PCB, VRM, AC >>toDC >converter), is very much a part of the power
> integrity problem. Note >>>that 1 mOhm of DC resistance in this circuit
> consumes 10 watts of power >>>(I^2*R) and renders our delivery system only
> 90% efficient. Power >>>Integrityinvolves delivering high current with
huge
> transients. It is >best >>understood and managed by the concept of target
> impedance in the >frequency >>domain. >>Signal integrity, on the other
hand,
> always involves signal nodes. >>A >few years ago, at the 50 MHz level,
> signalintegrity basically meant >the >>waveform quality and timing on
ideal
> transmission lines. Before >that, all >>wehad to worry about (at the 5 MHz
> level) was RC time >constants. Now we are >>beyond 500MHz where we must be
> concerned with >frequency dependent loss and >>return current paths.
Several
> years ago, >SSN (simultaneous switch noise) >>wasmostly an L*di/dt problem
> that >created ground bounce in the DIP's (dual >>inline packages, lead
> >frames). After we started including ground planes in >>our packages,
> >replaced wire bonds with solder bumps and started using just >>as many
> >ground pins as signal pins, the SSN problem changed to a power
> >>plane>bounce and return current problem. This is how power integrity
keeps
> >>>getting mixed up with signal integrity. The return current for signals
> >is>>on power and/or ground planes. But we can avoid a lot of confusion
>if
> we >>usethe term "power integrity" for topics that involve just Vdd >and
> ground >>and reserve "signal integrity" for topics that involve >signal
> nodes. >>>>Decoupling capacitors play a role in all three topics. For the
> power >>>integrity problem, they are energy storage devices that mitigate
> power >>>transients. They deliver energy when the voltage droops and store
> >energy >>when the voltage spikes. For the signal integrity problem, they
> >enable >>return current to jump from one node to another (i.e. Vdd1 to
> >Vdd2or Vdd >>toGnd) when packages, vias or connectors require signal
> >returncurrent to >>make the jump. For the EMI problem, they provide low
> >impedance and energy >>absorption at frequencies where the product
> >naturally has a lot of energy >>(clock) or frequencies where the product
> >has a very efficient resonator or >>radiator. >>Decoupling capacitors are
> effective for the power integrity >>problem in >the 100 kHz to 100 MHz
> frequency band. Below 100 kHz it takes >>toomany >uF for them to be
> effectiveand above 100 MHz their inductance gets >>in >the way. However,
> decoupling capacitors may be used to complete return >>>current paths (SI)
> orabsorb noise (EMC/EMI) up to much higher >>>frequencies.Below 50 MHz,
> position on the PCB is not very important >but >>above 200 MHz, position
> often becomes critical. Thin power plane >>>dielectricsare a good
> replacementfor discrete decoupling >capacitors that >>are aimed at
> frequencies above 100 MHz. Power plane >capacitance is "broad >>band" but
> theQ of discrete capacitors becomes >sharp and limits their
>>effectiveness
> as frequency increases. >>Very few topics on SI-list seem to >>evoke as
many
> emotions as decoupling >capacitors. That is probably because >>people view
> them from so many >different perspectives. Vastly different >>conclusions
> canbe drawn for >decoupling capacitors depending on the problem >>you are
> trying to solve >(PI, SI or EMI) and other variables such as power >>plane
> dielectric >thickness. Some of this can be helped by clearly defining
>>the
> >terminology and use conditions. >>regards, >Larry Smith >Sun
>>Microsystems
> >>>Delivered-To: si-list@xxxxxxxxxxxxx >>From: "Grasso, >>Charles">>To:
> "'si@xxxxxxxxxxxx'" , "'si-list@xxxxxxxxxxxxx'" >>>Subject: >>[SI-LIST]
Re:
> UltraCAD ESR and Bypass Capacitor Caculator >>Date: Thu, 14 >>Aug2003
> 15:39:34 -0600 >>MIME-Version: 1.0 >>Content-Transfer-Encoding: 8bit
> >>>>X-archive-position: 7937 >>X-ecartis-version: Ecartis v1.0.0
> >>>>X-original-sender: Charles.Grasso@xxxxxxxxxxxx >>X-list: si-list
>>>>Hi
> >>Kim, >>First - thanks for putting the slides up on the bweb for >>all to
> >>see.I think that you may have missed the point >>a little. In your
> scenario>>(a signal trace switching >>planes )the location of the caps is
> vital. >>>>>>The discussion was centered on the location of caps >>wrt
power
> >>distribution. The location of the capacitors >>(within reason) will not
> >>affect a S11/S21 measurement >>that much. >>>>Fancy tackling that little
> >>problem? >>>>Best Regards >>Charles Grasso >>Senior Compliance Engineer
> >>>>Echostar Communications Corp. >>Tel: 303-706-5467 >>Fax: 303-799-6222
> >>>>Cell: 303-204-2974 >>Email: charles.grasso@xxxxxxxxxxxx; >>Email
> >>Alternate:chasgrasso@xxxxxxxx
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