[SI-LIST] Re: 6 Layer Stack-up
- From: "John Matthews" <john.matthews@xxxxxxxxxxxxxxxxx>
- To: <chris.cheng@xxxxxxxxxxxx>
- Date: Tue, 16 Sep 2003 10:21:45 +0100
Chris
Definitely worth thinking about, I think that the reason I didn't go that
way in
the first place was that I thought I would have better decoupling if power
and
ground were adjacent.
Of course I neglected the fact that top and bottom would not have reference
planes,
which was partly corrected second time round with the copper fills.
There seems to be a bit of compromise involved. We fix one problem at the
expense of
another.
John
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Cheng
Sent: 15 September 2003 21:33
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: 6 Layer Stack-up
John,
Why not S-P-S-S-G-S and bury all your fast signals inside ?
-----Original Message-----
From: john.matthews@xxxxxxxxxxxxxxxxx
[mailto:john.matthews@xxxxxxxxxxxxxxxxx]
Sent: Saturday, September 13, 2003 3:57 PM
To: chris.cheng@xxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: 6 Layer Stack-up
We recently completed a board, having had a lot of trouble with EMI.
We started with S-S-P-G-S-S (layers 1-2-3-4-5-6) and found that our
emissions (radiated) were such that we didn't have a hope in hell of
passing Class B.
We then modified the board components single sided) in the following way:
1.. We identified the slowest and fastest signals.
2.. Fastest signals went on layers 2 and 5, preferably layer 5.
3.. Slowest signals went on layers 1 and 6.
4.. On layer 6, we took extreme care to lay out the slow signals,
such that we could copper fill afterward and then stitch around the
edge of the board to the ground plane. We took care of the slow
signals so that they didn't cut the copper fill too much, i.e.
localised them and kept them in one dimension.
5.. We did something similar with Side 1, althouth this isn't as effective
since we've too much discontinuity with component bodies.
The result was that we can pass emissions testing now. However it meant we
had to hand route the board (lots of work).
I'm trying to learn lessons from this to carry into future designs. The
flooding definitely helped. We did it beacuse we knew that we would pass
test if we put our board on a metal box, rather than plastic, so we though
why not try to get some of the Farady effect on the PCB itself.
I agree with the point that the noise is still there .. you can't get rid
of harmonics as you need them for SI, so they'll come out somewhere. In
our case, it looks as of our cables are a bit nosier ..
I'm interested in comments. we had loads of decoupling, but even using
10pF decouplers could not get rid of the higher harmonics.
John
> In reality people stitch ground vias along the edge of the PCB to form a
> faraday cage to confine the stripline radiation within the PCB.
> -----Original Message-----
> From: Ravinder.Ajmani@xxxxxxxx [mailto:Ravinder.Ajmani@xxxxxxxx]
> Sent: Friday, September 12, 2003 7:22 PM
> To: chris.cheng@xxxxxxxxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Re: 6 Layer Stack-up
>
>
>
> Yes, that is what I also get when I do EMI simulation with MoM simulator.
> However in actual practice, you can't control EMI by simply burying it
> between planes. The energy will always find a way to come out and
> radiate.
>
> Regards, Ravinder
> Server PCB and Flex Development
> Hitachi Global Storage Technologies
>
> Email: Ravinder.Ajmani@xxxxxxxx
>
>
>
>
>
> Chris Cheng <chris.cheng@xxxxxxxxxxxx>
> Sent by: si-list-bounce@xxxxxxxxxxxxx
>
>
> 09/12/2003 01:50 PM
> Please respond to chris.cheng
>
>
>
> To:
> cc: si-list@xxxxxxxxxxxxx
> From: si-list-bounce@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: 6 Layer Stack-up
>
>
>
>
>
> Not necessary true.
> The key is what signals do you put on the microstrip layer that is
> reference
> to P-plane. If you are stupid enough to put highspeed signals that has
> nothing to do with P-power on it, they will need a return path and will
> most
> likely exhibit itself as ground/power bounce on signals and high EMI
> radiation. In that case S-S-P-G-S-S provides the lower impedance return
> path
> through the plane capacitance. But that's not as good as if you bury the
> highspeed signals as striplines inside the S-P-S-S-G-S stackup. I can
> easily
> show you example of bad EMI when I force highspeed signals on the
> outer-layer referencing a power plane that has nothing to do with I/O
> power
> and how it can be "improved" with a thin core P-G added. But I can also
> shows you if I bury them as stripline, the EMI will be even better than
> with
> thin core.
>
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
