Weston,
There is very simple reason to treat all ports of a multiport as single
terminals in the circuit analysis.
Let's start from the basic definition of port. It is two terminals with
identical currents flowing in opposite direction. If two terminals are signal
and reference terminal, current to the signal terminal must be equal to the
current from the reference terminal - this is by definition and must be
enforced. A multiport descriptor of immittance type (Y, Z matrices or other
type) relates the voltage between the terminals with these currents.
S-parameters are defined with the linear combination of port current and port
voltage (waves) and describe power flow through port. Connected ports must have
exactly the same signal and reference terminals (continuity condition). This
and the opposite current requirement defines all possibilities and restrictions
for the circuit analysis, as well as all possibilities and restrictions for the
port manipulations.
Circuit analysis possibility #1 - all reference terminals of a multiport are
connected to a common reference - this is the simplest option that does not
violate port definition. Ports can be represented with just the signal
terminals in this approach. If all ports are properly defined with the physical
coincidence of the signal and reference terminals at all connections, the
common reference automatically becomes the global reference. Circuit voltage at
the reference terminals is always zero (or constant) with this approach - this
is not a limitation, but rather consequence of the port definition. All ports
may have completely different reference conductors or local references with
this approach too - it may be counterintuitive, but can be proved. The only
thing we are missing with this approach is the relative voltages between
reference or signal terminals - that cannot be gained with any other approaches
- see simple example below.
Possibility #2 is to use separate reference terminal for each port in the
circuit simulation - this doubles the number of variables but does not increase
the accuracy of analysis or get us any new information about the system. This
is because of the multiport descriptor relates only the difference of the
voltages at the terminals and because of limitations on possible ways you
connect the reference as well as the signal terminals. Any such connection must
preserve the current equality at terminated or connected ports and the opposite
currents through the reference. All connections that violate this will produce
incorrect results. The only case when separate referencing may be needed is
when someone needs to set DC bias for non-linear components and that only in
cases when series ports are used to connect such components. The DC bias in
this case have to be set externally - not come from the multiport circuit. I do
not know other cases when it may be useful.
The meaninglessness of the use of separate reference terminals becomes obvious
if you look at the following simplest case - two-port link with port 1 defined
between terminals P1 and G1 and port 2 between P2 and G2 and two resistors
connected between P1 and P2 and between G1 and G2 as follows:
P1--R1--P2
G1--R2--G2
This would be a DC approximation of a t-line segment with signal conductor
resistance R1 and the reference conductor resistance R2.
The admittance matrix for that 2-port structure is
Y11=Y22=1/(R1+R2);
Y12=Y21=-1/(R1+R2)
Can you see a problem with the separation of the terminals here?
If you use Y or S-matrix to simulate this, no matter what you do in a circuit,
you will never be able to separate R1 and R2 from the sum of them that is in
the multiport parameters. Also, association of the local reference with the
global one will not neglect the information about ground resistance R2 - it is
already in the multiport parameters. The relative port voltages and currents
will be correct, though, there is no way to recover voltage difference between
G1 and G2 (and between P1 and P2 if that matter).
To be able to treat the reference nodes separately and have voltages at all
terminals at least at DC, the following definition must be used
P1--R1--P2
P3--R2--P4
G1-------G1
Port 1 is P1 to G1, port 2 is P2 to G1, port 3 is P3 to G1 and port 4 is P4 to
G1. If you write down Y-matrix for this 4-port structure, you will see that R1
and R2 are not together and the matrix can be reduced to the 2-port matrix with
combined R1+R2 or used directly to have voltage drop in the reference net
explicitely.
Best regards,
Yuriy
Yuriy Shlepnev, Ph.D.
President, Simberian Inc.
www.simberian.com
Simbeor – Accurate, Productive and Cost-Effective Electromagnetic Signal
Integrity Software to Design Predictable Interconnects!
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Beal, Weston
Sent: Monday, December 2, 2019 6:12 AM
To: Muranyi, Arpad; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: 3d modelling of high frequency signals with dual
referencing
Arpad,
The terminals of the ports are much easier to play around with in simulation
than in hardware measurement. That's true. Since your task is to write a
specification that can apply to both measured and simulated S parameters, it is
important to support the slightly limited port definitions of measurements.
Also, since most simulators define the S-parameter circuit blocks with one
terminal per port, the selection of the reference terminal becomes more
important. I think it makes sense to stick with the traditional sense of GND
(or VSS) for the reference terminal. This structure is usually the largest
conductor structure so will be the reference for more other metal structures.
Regards,
Weston
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Muranyi, Arpad
Sent: Wednesday, November 27, 2019 2:18 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: 3d modelling of high frequency signals with dual
referencing
Weston,
Thanks for your reply. I liked you comment on the DC point!
You are making excellent points, and I agree that there are many different ways
of defining the ports for my hypothetical example. In your first paragraph,
you were discussing the pad side and said "It doesn't even matter which pad you
use.". I agree with that too, in theory. But in practice and from the
perspective of a standardization effort (IBIS), things can get more challenging.
Let's apply your "doesn’t matter" statement to the pin side. The model will
most likely be connected to other S-parameter models at the pin interface, such
as the models of the board interconnects. If I am not mistaken, the general
rule is that when ports are connected to each other from different S-parameter
models, they must have the same reference. What can we (IBIS spec, EDA vendor,
model makers) do to make sure that this requirement is satisfied when the
package and board model may come from different sources using different
extraction tools, etc.?
Thanks,
Arpad
==================================================================
-----Original Message-----
From: Beal, Weston
Sent: Wednesday, November 27, 2019 1:49 PM
To: Muranyi, Arpad <Arpad_Muranyi@xxxxxxxxxx>; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: 3d modelling of high frequency signals with dual
referencing
Arpad,
S-parameter ports can be confusing, especially because so many tools represent
the port with one terminal. If we simply change the view to have 2 terminals on
every port then the topic is less confusing but more surprising. Looking at
just one end of the configuration in your example, you could use one of the
pads as a reference for the other 2 pads. It doesn't even matter which pad you
use. Or you could use VSS pad for the reference terminal of the signal port and
the signal pad as the reference for the VDD port. At this point it is very
important to connect the block into the circuit in the same way that the ports
were connect to the DUT for measurement or simulation. Another possibility (for
simulation) is to use the universal ground as the reference for 3 ports. Just
make sure you connect the S-parameter block this same way into your circuit.
Make sure you don't short the wrong reference terminals or you will nullify
some portion of the S-parameter block.
One important thing to remember is that the reference terminal does not have to
be the same for all the ports of an S-parameter block. Each port has its own
reference. The connections of the terminals need to be clearly documented for
the S parameters to be useful.
Another complication is the way that your chosen simulation tool represents the
S-parameter ports. If your simulator's circuit definition uses only one
terminal for each port then the reference terminal for all ports is the
"ground" node. Therefore, your S parameters have to be measured or simulated
with the port reference terminals connected to something that represents ground.
Your last statement brings up another issue, behavior at 0Hz. Most S parameters
are not measured or simulated to very low frequency. The simulator has to
extrapolate to DC for transient simulations, and the extrapolation might not go
well. Different tools will reach different extrapolated values because of
different algorithms and assumptions. Maybe part of your standard should define
that [S, Z, Y] parameters need to be correctly specified at 0Hz.
Regards,
Weston
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Muranyi, Arpad
Sent: Wednesday, November 27, 2019 1:18 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: 3d modelling of high frequency signals with dual
referencing
Hello Everyone,
Now that I see many of our experts participating in this conversation, I would
like to ask a related question, even though it might deviate a little bit from
the original post.
This came up in the conversations in the IBIS Interconnect Task Group when we
were working on the new interconnect modeling syntax for IBIS v7.0 (also known
as BIRD189).
For simplicity, imagine a device with three pins which has a die with three
pads. One for Vdd, one for Vss and one for the signal. Let's say you want to
extract an S-parameter model for the package that goes between the pins and
pads. How many ports is this S-parameter model going to have, and where would
the reference terminal of each port be connected? Assuming a regular CMOS
buffer on the die, keep in mind that the buffer will sometimes put a low
impedance current path between the signal and Vdd and other times between the
signal and Vss, and consequently the currents need to be accounted for properly
for both conditions.
Thanks,
Arpad
====================================================================
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
