Hi Amit,
Given the referencing, you of course need to have both power plane and ground
plane layers included in your extraction. Next, you will need to make sure
that you have the decap models loaded before extraction. Such that you have
provided an AC path between gnd and pwr.
Next you setup your ports. The best and simplest thing to do is look at what
is the closest metal to your data line, try to picture how the field lines
would setup. Sometimes it is as easy as just seeing where the closest pwr or
gnd pin is, and following your eye to the plane above or below.
In some cases like a DIMM card, it is pretty clear that VDD is the signal
return path for your Command Address pins. The power plane is directly below
the command address gold-fingers, and the ground gold-fingers are much further
away.
To setup your EM port you make sure you have a plus pin on the signal, minus
pin on the closest pwr/gnd that makes sense. The further your + and - are away
from each other, the larger the parasitic inductance, which will affect your
results at higher frequencies.
Here's a video that visualizes the VDD being closer to the CA bus pin:
https://youtu.be/Qc1YjtzQfEU?t=74 ;(if SI-List blocks the link, please
contact me privately and I'll send it separately).
One interesting point to keep in mind, is that in DDR you often have more
signal pins than pwr or gnd pins. It may mean that you are sharing the
negative reference pin for multiple signals. That is ok, it is real life, as
those return currents are sharing the same pin and you will have increased
crosstalk as a result.
Finally on the topic of ports, each EDA vendor has a variety of different port
tools and calibration techniques. Some tools reduce the parasitics by using
sheet ports, some tools allow you to setup waveguide ports, or even add a PEC
gasket on top so that a coaxial port can be used. All will give different
improvements in high-frequency accuracy (above 20GHz). Discussion of ports can
be a complex topic though, because accuracy depends on what we are comparing
to. If you want measurement to match simulation you ought to setup ports in
the most similar way to how the device will be measured.
Hope this helps.
Best regards,
Stephen.
SI & PI Product Planner, PathWave ADS
Keysight Technologies
Santa Rosa, CA
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf Of
Amit Kumar
Sent: Tuesday, November 26, 2019 8:51 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] 3d modelling of high frequency signals with dual referencing
[EXTERNAL]
Hi SI/PI experts,
I have a question on 3d modelling of pcb/package signals with dual referencing
(let's say vdd and gnd) i.e. the signal trace layer is sandwiched between vdd
and gnd layers.
The port is defined between signal and gnd but the return current will also
flow through vdd.
What's the best way to capture the correct behaviour in this case?
Do we need to define the impedance between vdd and gnd while modelling?
It will be great if anyone could provide me some references on this topic.
Regards
Amit
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