[iyonix-support] Re: Serial port start-up issues
- From: John-Mark Bell <jmb202@xxxxxxxxxxxxxxx>
- To: iyonix-support@xxxxxxxxxxxxx
- Date: Mon, 1 May 2006 15:03:40 +0100 (BST)
On Sun, 30 Apr 2006, Dave Higton wrote:
> The data sheet for the 1535 Southbridge Controller, part 1, PDF p26,
> shows that pad H1 is an input while reset is active. If the pin is
> at logic 1, the configuration register's base address is 3F0; if 0,
> the configuration register's base address is 370. The pin has a 20k
> pull-up resistor. After release of reset, the pin becomes "RTS1J",
> the RTS output for UART port 1. Assuming the simplest circuit, and
> no other pull-down resistors, I'd expect this pin to be at a logic 1
> during reset, and therefore I'd expect the configuration register's
> base address to be 3F0. Is this what the Iyonix's software assumes?
I believe so. Note that this is the configuration register for the
SuperIO part of the SouthBridge (and not for UART1).
> How do we find out where the configuration register is? Can we use
> a HAL SWI to look? What command would that be?
I'm not aware of there being any API for accessing this.
> Is there any reason why RISC OS shouldn't look for both addresses,
> determine where the device has configured itself, and use that address
> from then on? Or even to use both addresses? (Easy for writes, more
> difficult for reads unless the read from the wrong address produces a
> consistent result.)
>
> I haven't got as far as figuring out the details of what the
> configuration register's base address means.
See part 3 of the datasheet.
The default physical addresses of the two UARTs' control register base are
&3F8 and &3E8 (as per most PCs). To access these you need to map them in to
logical space using OS_Memory 13 or 14 (note that they're probably already
mapped in, anyway).
Here's some example code for reading the physical address of UART 1:
DIM code% 1024
P%=code%
[OPT2
.inb%
MRS R1,CPSR
SWI "OS_EnterOS"
LDRB R0,[R0]
MSR CPSR_c,R1
MOV PC,LR
.outb%
MRS R2,CPSR
SWI "OS_EnterOS"
STRB R1,[R0]
MSR CPSR_c,R2
MOV PC,LR
]
REM logical port addresses (use OS_Memory 13/14 to look these up)
cfgp%=&F5A003F0:REM Phys &3F0
idxp%=&F5A003F0
datp%=&F5A003F1:REM Phys &3F1
REM enter cfg mode
A%=cfgp%
B%=&51
CALL outb%
A%=cfgp%
B%=&23
CALL outb%
REM select UART1 (device 4)
A%=cfgp%
B%=&07
CALL outb%
A%=datp%
B%=&04
CALL outb%
REM read base address (top)
A%=cfgp%
B%=&60
CALL outb%
A%=datp%
adt%=USR inb%
REM read base address (bottom)
A%=cfgp%
B%=&61
CALL outb%
A%=datp%
adb%=USR inb%
REM exit cfg mode
A%=cfgp%
B%=&bb
CALL outb%
PRINT~adt%;~adb%
John.
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