[ibis-macro] Re: Node "0" in IBIS, IBIS External Model, IBIS Interconnect Models
- From: Bradley Brim <bradb@xxxxxxxxxxx>
- To: "ibis-macro@xxxxxxxxxxxxx" <ibis-macro@xxxxxxxxxxxxx>, "ibis-users@xxxxxxx" <ibis-users@xxxxxxx>, "ibis-interconn@xxxxxxxxxxxxx" <ibis-interconn@xxxxxxxxxxxxx>
- Date: Wed, 6 Aug 2014 23:34:19 -0700
Hello all,
This is a message to solicit feedback to the IBIS interconnect task group. It
is not to initiate an extended e-mail exchange among this entire distribution
list. Please consider replying to
ibis-interconn@xxxxxxxxxxxxx<mailto:ibis-interconn@xxxxxxxxxxxxx> with any
thoughts you wish to share.
The interconnect task group has been working on a BIRD to enable more general
package/on-die interconnect models inside the IBIS topology through the
application of ISS subcircuits. ISS supports the application of global ground.
There is a vote scheduled for 8:00am this Wednesday August 13 in the
interconnect task group meeting to decide whether or not we allow access to
global ground for this new package/on-die interconnect modeling. We delayed the
vote because there are only a handful of active participants in this task group
and we wished to allow for broader comment before making such an important
decision. Views among the active participants vary, as we suspect they will
throughout the IBIS user/developer community.
Cadence believes that global ground should not be accessible from within IBIS
package/on-die interconnect models. We do not believe an industry standard
should allow access to any electrical node outside the topology of IBIS except
for connectivity through one of the formally declared external pins. Any
current that flows to global ground in the electrical model that does not
connect through a pin in the external pin list is non-physical and incorrect.
If global ground access is disallowed for these new models, a very small
incremental effort is required by model developers to apply package/on-die
interconnect models which now apply global ground (see examples below).
We believe it would be a benefit to the IBIS community to revisit the buffer
portion of the specification formally disallow access to global ground and
clarify all local references, such as to where C_comp or legacy package pin
capacitances are referenced. We perceive this activity as a separate, though
related, discussion and wish to focus now on the decision for interconnect. If
global ground is available in the new package/on-die interconnect portion we
perceive much less value in revisiting the buffer portion of the spec to
clean-up references and global ground issues.
Thanks in advance for sharing your thoughts with the interconnect task group,
-Brad Brim
The motion being considered is to disallow the application of global ground for
the new IBIS Package/On-die Interconnect modeling capability. The motion
addresses only the new section of the specification we are now considering.
Specifically, it does not resolve questions such as: to where is C_comp or a
legacy package pin capacitances referenced. Further, the motion does not
restrict the application of global ground for other present or future ISS
applications. The motion does not include a proposed implementation, though a
few alternatives are discussed below.
The only ISS element that implicitly applies global ground is the S-element in
its N-node form. The proposal could either (a) disallow application of this
form of the S-element, or (b) impose two requirements: (1) model maker
specification of a reference terminal to replace any occurrence of global
ground, and (2) EDA tool application of this terminal as local reference
instead of the implicit global ground.
It seems there are two potential implementations. One choice would be to
consider all occurrences of what would otherwise be global ground (i.e. '0',
GROUND, GND, !GND, GND!) as any other locally-scoped node. These nodes would be
connected to each other within the subcircuit but outside the domain of the
subcircuit would remain floating unless explicitly exposed in the external node
list and connected to something in a higher level circuit. The N-node form of
the S-element would be disallowed. Alternately, an implementation similar to
that described above as option (b) for the N-node form of the S-element could
be pursued.
It is likely a local reference terminal will require model maker specification
to enable termination of unused terminals for Package/On-die Interconnect
Models. This terminal could also serve as local reference for any explicit or
implicit formerly global ground if an EDA tool solution is pursued.
If the choice of explicitly exposing global ground nodes is chosen, then EDA
tools are not likely to require any changes for immediate support of this new
Package/On-die Interconnect modeling capability; except for the model developer
convenience feature being considered for terminating unused terminals. A small
incremental burden of exposing these nodes in subcircuit calls will be required
from model developers for all these new models. If the path of EDA tool mapping
of global ground to a local reference terminal is pursued, then all EDA tools
will require significant enhancement to support the new capability. Due to
development resource allocations and commercial release schedule
synchronization it is likely to require a year or more for the capability to be
broadly supported once the specification becomes available. The timeframe for
support of terminating unused terminals may be similarly long even for the
explicit exposure choice, though the effort seems significantly less because no
updating of model maker specified netlists will be required prior to internal
consumption by the EDA tool.
A ISS subcircuit could presently be referenced as
xThruPath in out
For any of the following cases
1. Node 0 global ground nodes
.subckt ThruPath 1 4
L1 1 2 1pH
L2 2 3 1pH
L3 3 4 1pH
C1 2 0 1fF
C2 3 0 1fF
.ends
2. Alternate global ground nodes
.subckt ThruPath 1 4
L1 1 2 1pH
L2 2 3 1pH
L3 3 4 1pH
C1 2 GND 1fF
C2 3 GROUND 1fF
.ends
3. Implicit reference node using global ground
.subckt ThruPath 1 2
S1 1 2 mname=thru
.model thru S 2 TSTONEFILE='TSthru.s2p'
.ends
4. Explicit reference node using global ground
.subckt ThruPath 1 2
S1 1 2 GND mname=thru
.model thru S 2 TSTONEFILE='TSthru.s2p'
.ends
5. Explicit reference nodes using global ground
.subckt ThruPath 1 2
S1 1 0 2 0 mname=thru
.model thru S 2 TSTONEFILE='TSthru.s2p'
.ends
6. Explicit reference nodes using various forms of global ground
.subckt ThruPath 1 2
S1 1 GND 2 GROUND mname=thru
.model thru S 2 TSTONEFILE='TSthru.s2p'
.ends
If the present global ground nodes ('0' and its aliases) are treated the same
as any other locally-scoped node with required explicit exposure in the
subcircuit node list, the above forms would change as follows:
1. Node 0 as global ground
xThruPath in out ref_node
.subckt ThruPath 1 4 0
L1 1 2 1pH
L2 2 3 1pH
L3 3 4 1pH
C1 2 0 1fF
C2 3 0 1fF
.ends
2. Alternate nodes as global ground
xThruPath in out local_ref local_ref
.subckt ThruPath 1 4 GND GROUND
L1 1 2 1pH
L2 2 3 1pH
L3 3 4 1pH
C1 2 GND 1fF
C2 3 GROUND 1fF
.ends
3. Implicit reference node using global ground would be a disallowed form.
4. Explicit reference node using global ground
xThruPath in out ref
.subckt ThruPath 1 2
S1 1 2 GND mname=thru
.model thru S 2 TSTONEFILE='TSthru.s2p'
.ends
5. Explicit reference nodes global ground
xThruPath in out ref
.subckt ThruPath 1 2 GND
S1 1 0 2 0 mname=thru
.model thru S 2 TSTONEFILE='TSthru.s2p'
.ends
6. Explicit reference nodes using various forms of global ground
xThruPath in out ref ref
.subckt ThruPath 1 2 GND GROUND
S1 1 GND 2 GROUND mname=thru
.model thru S 2 TSTONEFILE='TSthru.s2p'
.ends
From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx]
On Behalf Of Walter Katz
Sent: Tuesday, August 05, 2014 6:50 AM
To: IBIS-ATM
Subject: [ibis-macro] Node "0" in IBIS, IBIS External Model, IBIS Interconnect
Models
All,
There is currently a debate in the IBIS Interconnect meeting on the allowed
usage of Node "0" in the new IBIS and EBD Interconnect IBIS-ISS and Touchstone
models. There is a vote scheduled on August 13 in IBIS Interconnect to forbid
the use of Node "0" (aka GND, !GND and GROUND) in IBIS-ISS subckts reference by
IBIS interconnect models.
SiSoft does believe that there are circumstances where using Node "0" in
interconnect and I/O Buffer Models is problematic and should be avoided. The
IBIS Interconnect draft BIRDs allow the model maker to create interconnect
circuits without using Node "0", but we also think that the proposal to forbid
Node "0" should be defeated:
We believe that to "outlaw" node 0 would merely remove a convenient
simplification to the circuit equations, forcing an accounting for a bunch of
voltages and currents that don't matter in the first place.
However, this is an important opportunity to understand Node "0" in the context
of the IBIS I/O buffers, so that I/O buffers can be created or implemented
without using Node "0". I will simply point out a number of places in the IBIS
6.0 specification which explicitly reference SPICE Node "0" or "GND" ( I am
sure I missed a number of cases but this should indicate the magnitude of the
effort to remove the usage of Node 0 in the IBIS specification, or how to
create IBIS I/O buffers that do not use Node "0"):
1. Page 93, 6.3 Multilingual Model Extensions:
a. A_gnd is a universal reference node, similar to SPICE ideal node "0."
Ports 14 and 15 are only available under [External Model] for support of true
differential buffers.
b. Can multilingual models be written without using A_gnd, and connect
this terminal of the multilingual model directly to a Signal_name defined in
the Component [Pins] list?
c. Also not Page 121, 6.3
i. One of
these port entries must name a reference for the other port (for example,
A_gnd).
d. Also note page 125
i. Ports vcc gnd io1 io2
e.
2. Page 33, 6.1 Model Statement
a. C_comp_pullup, C_comp_pulldown, C_comp_power_clamp, and
C_comp_gnd_clamp are intended to represent the parasitic capacitances of those
structures whose I-V characteristics are described by the [Pullup], [Pulldown],
[POWER Clamp] and [GND Clamp] I-V tables. For this reason, the simulator
should generate a circuit netlist so that, if defined, each of the C_comp_*
capacitors are connected in parallel with their corresponding I-V tables,
whether or not the I-V table exists. That is, the C_comp_* capacitors are
positioned between the signal pad and the nodes defined by the [Pullup
Reference], [Pulldown Reference], [POWER Clamp Reference] and [GND Clamp
Reference] keywords, or the [Voltage Range] keyword and GND.
3. Page 51, 6.1 Model Statement
a. C_comp_pullup, C_comp_pulldown, C_comp_power_clamp, and
C_comp_gnd_clamp are intended to represent the parasitic capacitances of those
structures whose I-V characteristics are described by the [Pullup], [Pulldown],
[POWER Clamp] and [GND Clamp] I-V tables. For this reason, the simulator
should generate a circuit netlist so that, if defined, each of the C_comp_*
capacitors is connected in parallel with its corresponding I-V table(s),
whether or not the I-V table(s) exist(s). That is, the C_comp_* capacitors are
positioned between the signal pad and the nodes defined by the [Pullup
Reference], [Pulldown Reference], [POWER Clamp Reference] and [GND Clamp
Reference] keywords, or the [Voltage Range] keyword and GND.
4. Page 56,..., Model Statement
a. The effective current table for the Isso_pd current is extracted by the
following process. The buffer is set to "logic zero." A Vtable voltage source
is inserted between the [Pulldown Reference] node and the buffer as shown in
Figure 7. This Vtable voltage is swept from -Vcc (typical) to +Vcc (typical)
and is relative to the [Pulldown Reference] typ/min/max values for the
corresponding columns. The output is connected to the GND (typical) value as
shown in Figure 7.
b. The effective current table for the Isso_pu current is extracted by the
following process. The buffer is set to "logic one". A Vtable voltage source
is inserted between the [Pullup Reference] node and the buffer as shown below.
This Vtable voltage is swept from -Vcc (typical) to +Vcc (typical) and is
relative to the [Pullup Reference] typ/min/max values for the corresponding
columns. The output is connected to the GND (typical) value as shown in Figure
8.
c. For example, for a typ/min/max [Voltage Range] of 5.0V, 4.5V and 5.5V,
and with the negative reference set to GND, the Isso_pu(0) and Isso_pd(0)
values for typ/min/max should be equal to the column values as shown in
d. Description: The data for these keywords define the resistance
values of Rgnd and Rpower connected to GND and the POWER pins, respectively,
and the resistance and capacitance values for an AC terminator.
e. Other Notes: [Rpower] is connected to "Vcc" and [Rgnd] is connected
to "GND". However, [GND Clamp Reference] voltages, if defined, apply to
[Rgnd]. [POWER Clamp Reference] voltages, if defined, apply to [Rpower].
Either or both [Rgnd] and [Rpower] may be defined and may coexist with [GND
Clamp] and [POWER Clamp] tables.
f. Figure 16 illustrates a general configuration from which a [Rising
Waveform] or [Falling Waveform] is extracted. The DUT die shows all of the
available power and ground pin reference voltage terminals. For many buffers,
only one power pin and one common ground pin terminal are used. The absolute
GND is the reference for the V_fixture voltage and the package model equivalent
network. It can also serve as a reference for C_comp, unless C_comp is
optionally split into component attached to the other reference voltages.
g. Other Notes: Figure 17 documents some expected internal paths for a
useful special case where only one common power pin (VDDQ) and one common
ground exists (GND).
h. The power reference terminal (VDDQ) is usually the [Pullup Reference],
or the default [Voltage Range] terminal. The [Pulldown Reference] terminal is
usually at the GND connection.
i. In most cases six [Composite Current] tables are recommended for
accurate modeling. The first four tables correspond to the recommended fixture
conditions for [Rising Waveform] and [Falling Waveform] tables (normally 50 ohm
loads to Vdd and GND).
j. The [Composite Current] table can be derived from currents measured
at the [Pulldown Reference] (GND) node, but adjusted for the current flowing
through the output pin and at other terminals.
5. There are a number of Figures that include a GND symbols, or a GND node
a. Examples.
i. Page 57,
6.1 Model Statement, Figure 7
ii. Page 72,
6.1 Model Statement, Figure 16
6. Page 162 ..., 9. Notes on Data Derivation Method
a. Then: Attach a 50 ohm resistor to GND to derive the rising edge ramp.
Attach a 50 ohm resistor to POWER to derive the falling edge ramp.
b. Then: Attach either a 50 ohm resistor or the semiconductor vendor
suggested termination resistance to either GND or the suggested termination
voltage. Use this load to derive both the rising and falling edges.
Walter
Walter Katz
wkatz@xxxxxxxxxx<mailto:wkatz@xxxxxxxxxx>
Phone 303.449-2308
Mobile 303.335-6156
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