Minutes from the 05 Aug 2014 ibis-atm meeting are attached. Thanks to Curtis Clark for taking minutes.
Mike
IBIS Macromodel Task Group
Meeting date: 05 August 2014
Members (asterisk for those attending):
Agilent: Fangyi Rao
Radek Biernacki
Altera: * David Banas
ANSYS: Dan Dvorscak
* Curtis Clark
Avago (LSI) Xingdong Dai
Cadence Design Systems: * Ambrish Varma
* Brad Brim
Kumar Keshavan
Ken Willis
Ericsson: Anders Ekholm
Intel: * Michael Mirmak
Maxim Integrated Products: Hassan Rafat
Mentor Graphics: * John Angulo
* Arpad Muranyi
Micron Technology: * Randy Wolff
Justin Butterfield
QLogic Corp. James Zhou
Andy Joy
SiSoft: * Walter Katz
Todd Westerhoff
Mike LaBonte
Teraspeed Consulting Group: Scott McMorrow
* Bob Ross
The meeting was led by Arpad Muranyi.
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Opens:
- Mike LaBonte unable to attend. Curtis Clark to take minutes.
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Call for patent disclosure:
- None
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Review of ARs:
- Arpad - Work with Randy to update BIRD 173.
- In progress via email.
- Bob and Ambrish - Update BIRD 147.
- Bob - Baseline uploaded to reflector. In progress.
- Ambrish - Examine BIRD 128 for possible BIRD 147 updates.
- Ambrish - I would like to discuss it today.
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New Discussion:
Global Ground in Interconnect Modeling:
- Arpad - [calling attention to an information posted in the agenda]
- There is a proposal on the table to not allow the usage of node 0 for
package and interconnect modeling in IBIS_ISS subcircuits.
- If interested, attend the upcoming Interconnect Task Group (ITG) meeting.
- Walter - I sent an email earlier. I think its content is important.
- IBIS itself is very unclear on the use of global ground and ground local
to the buffer.
- IBIS would need some clarifications for SSO and PI simulations.
- This issue is not limited to interconnect models only.
- MM - We had a discussion in the ITG meeting about what Walter described.
- There are many locations where node 0 is referenced in IBIS itself.
- Brad - ITG not referencing the general IBIS inconsistencies.
- What's on the table for discussion is only to disallow node 0 for the
new packaging models.
- Walter - Brad, you agree that IBIS should look into it, right?
- Brad - Yes.
- Arpad - If no other questions, let's jump down to item #7 on the agenda.
BIRD 173:
- Arpad - Randy wrote BIRD 173.
- We got feedback from Vladimir at Mentor on more comprehensive rules.
- Agenda item includes a brief overview of Vladimir's rules [below]:
#a) Assumption is that the package RLC structure is passive, which
necessitates positive definite matrices from which come the
following requirements for the matrix elements. We could also
mention that coupling or losses due to L and R are associated
with current (through variable), but coupling in C is associated
with voltage (across variable), which is why there are differences
in the rules between them.
#b) Matrix C should belong to the class of M-matrices, but L and R
should be inverse M-matrices. All should be positive definite.
See e.g. http://en.wikipedia.org/wiki/M-matrix about M-matrices.
#c) Symmetry must be assumed for all of them: R, L, C.
#d) Off-diagonal entries of the capacitor matrix should be non-positive.
Diagonal entries should be non-negative. In addition, diagonal
entries should make 'diagonal dominance': each element on the
diagonal should be larger than the sum of modules of the non-diagonal
components in the same row or same column. This condition ensures
the capacitance matrix be positive-definite, and the RLC structure
passive. Non-passivity should not be allowed.
#e) Diagonal elements of the inductance matrix should be non-negative
(positive or zero). Each diagonal element should be larger than
absolute values of any of the non-diagonals that belong to the same
row or column. Matrix L should also be positive definite (all its
eigenvalues are positive or zero), but this condition is more difficult
to check than for C-matrix. Possible check: find the matrix X=inv(L).
Then, X should satisfy the same criteria as was stated for capacitance
matrix C.
#f) Resistance matrices have the same requirements as the inductance
matrices.
In many cases, however, we don't consider mutual resistance, in which
case R becomes diagonal matrix.
- Please read them and provide feedback.
BIRD 128:
- Ambrish - I brought BIRD 128 from .txt to .doc format.
- Propose to change AMI_parameters_out to AMI_parameters_inout.
- Added description text.
- API unchanged [parameter order].
- AMI model now also capable of reading things from this string parameter.
- Everything is the same except that in output mode the EDA tool zeroes the
pointer [contents of the **] after every AMI_GetWave() call. That won't
work in input mode.
- Walter - Just to clarify.
- In IBIS 7.0 (when this is included), when the EDA tools call AMI_GetWave()
(Tx or Rx), they should set the contents of that ** to null if they're not
sending anything in.
- Arpad - Question, this being in/out, do we need to define when it can be used?
- Do we need to define when it's an input and when it's an output?
- Avoid both sides writing to it at the same time?
- Walter - That's a difficult question.
- We could say if the AMI includes BCI then assume model will look at input.
- Ambrish - The EDA tool calls AMI_GetWave().
- So the EDA tool knows when to read from and/or write to the string.
- Walter - But how does the EDA tool know that AMI_GetWave() is going to look?
- Ambrish - It doesn't know.
- Walter - How does it know if it has to write something for the model to read?
- Ambrish - It needs to write the BCI string.
- Walter - So if the model includes BCI then the EDA tool knows it has to write.
- There may be other Tx <--> Rx communication schemes not in a BCI file.
- You're defining one way of doing it, but we will want to define others.
- Other ways may use the same approach.
- Arpad - My concern is whether these rules are spelled out.
- When it's an input, when it's an output, when it's i/o?
- Ambrish - It's an input before the AMI_GetWave() call.
- It's an output after the call.
- Bob - Does ami_parameters_out go away?
- Arpad - Yes, it's just renaming the parameter.
- Bob - It doesn't impact existing models?
- Walter - It's analogous to a spice subcircuit.
- You have a terminal called ABC, and we're renaming that terminal inside the
subcircuit.
- Bob - Okay.
- We should get the BIRD rev #, date, etc. into the draft.
- Walter - Ambrish, you should add yourself to the list of requestors.
- Bob - Usage of this is not limited to BCI, so it should stay a separate BIRD.
BIRD 147:
- Ambrish - Bob may still be working on it.
- Arpad - Is the version posted to the reflector finalized?
- Bob - We are working on it.
- The version on the reflector is the reorganized version of the older
BIRD147.
- Defines reserved branches, etc.
- I will work with Ambrish more offline.
- Arpad - I'm just wondering about the next step?
- BIRD 128 to Open Forum?
- BIRD 147?
- Bob - We still need to discuss BIRD 147.
- Arpad - Should we keep BIRD 147 on the agenda?
- Should we vote BIRD 128 out of this committee and take it off the agenda?
- Ambrish - I actually said I would mail it to Mike LaBonte for the reflector.
- But, I can send it to Michael Mirmak.
- Walter - Ambrish, I suggest you send it to Michael Mirmak to get a rev #.
- Next week we can vote to send it to the Open Forum.
Ambiguous Directionality (BUG150):
- Arpad - Michael [Mirmak], do you have any updates for us on directionality?
- MM - No updates.
- I have to go back through my notes.
- A couple of cases were not addressed.
New Redriver BIRD:
- Arpad - Same question for Walter. Anything new on this?
- Walter - As soon as we close discussions of BIRD147, or have free time.
- Certainly I need Fangyi and Radek.
- When you only have AMI_Init() models then IBIS6.0 is clearly incorrect.
- This BIRD corrects this.
- Very complicated when you have a mix of Init() and GetWave() models.
- Fangyi and I went back and forth many times.
- We may never get to consensus, but we can highlight the issues.
- Fangyi and I need to prepare for that.
- Table this for at least two meetings.
- Arpad - Alright.
Handling of missing min/max data:
- Arpad - I started this topic.
- Did we come up with any resolution on whether we should do anything?
- Current IBIS spec allows all combinations of providing or not providing
min or max data.
- For IBIS curves, ISSO, etc., these combinations may not make sense.
- Should we publish rules linking them in terms of min and max?
- Walter - I think the problem is much simpler, let's make it simpler.
- A model should not [ideally] be missing data in any min or max column.
- If a model does not have all the data in a min or max column, then one
should use min or max at their peril.
- The only thing the model maker is really supporting is typ in that case.
- Arpad - That is definitely a simplification. I'm open to that suggestion.
- Arpad - Any other comments? [none]
- I will take the AR to go over the spec and see how much work it would take.
- Bob - If it's one basic rule, no need to go through the whole spec.
- Arpad - In some places it says, "if min is missing, use typ..."
- In other places it doesn't say anything.
- Delete them all, or change them all to the same sentence?
- Bob - Change them all to the same sentence.
- There are cases where it is okay to just use typ.
- Voltage references for ECL, where the pullup is always the same voltage.
- I'd prefer just a simple rule rather than a bunch of changes.
- Arpad - I will go through the spec. Then we can continue the discussion.
- Bob - Okay.
- Arpad - That's the last item on today's agenda.
- Unless we have any questions or want to untable something...
- Bob - Will we talk about node 0?
AR: Arpad to review spec for min max issues.
Over-clocking:
- Arpad - Actually, I would like a motion to untable the over-clocking topic.
- MM - Motion to untable the over-clocking topic.
- Arpad - Second.
- I would like to see if Cadence can give us more technical details on their
over-clocking solution.
- Brad - No more details are available today.
- I can check with people.
- Arpad - Thanks, I'd appreciate any update.
Global ground:
- Ambrish - About the global ground, can someone fill us in on that?
- MM - I can tackle that.
- Two intertwining issues:
- Proposal in ITG: Since package and possibly on-die models will link to
IBIS buffers, there is interest in explicitly not supporting global ground
in interconnect models.
- If you have a reference it has to be explicitly passed from a pin.
- Related question: How is IBIS today using ground?
- Cursory review shows it's unclear what ground is being described.
- It strongly implies the EDA tool's global ground in some places.
- We would like to cleanup IBIS in general and this in particular.
- Ambrish - So, when IBIS started, assuming global ground was probably okay?
- Are we now seeing lots of problems with global ground?
- Is that the issue here?
- Arpad - Now that we're doing power integrity, it's extremely important.
- We need to account for where the currents are really flowing.
- Using ideal grounds means current doesn't go in the proper path.
- Ambrish - Are we saying it's time to fix IBIS or is it too late?
- MM - We have a proposal to discuss it and clarify usage.
- Prohibit the use of node 0 for on-die and package interconnect.
- How does that affect IBIS buffers?
- We at least need to understand where node 0 is used in IBIS.
- Arpad - There are two aspects.
- Immediate: In current interconnect work using IBIS ISS, we disallow node 0.
- It defeats the purpose of PI analysis.
- With buffer modeling we are in okay shape with IBIS in general.
- We have four IBIS I/V curves, each with their own supply reference.
- If you use the C_comp splitting parameters then you're okay.
- If you use regular C_comp then it is ambiguous.
- MM - If you use multiple independently referenced C_comps and pin mapping then
you're pretty good.
- If not, then it is unclear.
- Walter - Here's the heart of the issue.
- If you have a buffer (real Silicon) all its transistors and other circuitry
are referenced to a local ground.
- It's not clear what that node is on every IBIS buffer.
- Ex. If Pulldown and Ground Clamp have separate reference nodes, which is
global ground?
- We need to figure out how to clarify definitions and explain how to hook it
up when you only want to use a local ground (not global) for that instance.
- For the interconnect it's up to the model maker to figure out how to get the
grounds defined.
- VSS can have multiple nodes on die and the interconnect circuit.
- Any of those nodes can be used from the die, or the pins can be terminals
on the interconnect circuit.
- Can supply power properly from pins to buffers and return currents back.
- Arpad - That's a good stopping point for today. Thank you all for joining.
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Next meeting: 12 August 2014 12:00pm PT
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IBIS Interconnect SPICE Wish List:
1) Simulator directives
