Michael,
Michael,
Minor detail on the last bullet of slide 5: add pad_name.
- Explicit identification of interconnect terminals by pin_name,
pad_name, signal_name or even [Pin Mapping] bus_label
Also, without getting into a long discussion, the expansion of slide 8a
options seems to stress that for some analysis we are encouraging that
several Sets be selected at once. That is possible. However, the
recommendation is that each Set contain all of the terminals and reference
electrical models (e.g., add the PDN [Interconnect Model] to the I/O
[Interconnect Model]s in a single set) - if that is what the model provider
had intended for the complete analysis.
I would add the simple bullet:
- Can support complete analysis intended by model deveioper with
one Set
This is consistent with the recommendation in the Spec. and avoids the
implication that we are encouraging several Sets to be combined in some
manner.
Bob
From: ibis-interconn-bounce@xxxxxxxxxxxxx
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Mirmak, Michael
Sent: Wednesday, January 25, 2017 4:23 PM
To: Walter Katz; IBIS-Interconnect
Subject: [ibis-interconn] Re: IBIS Interconnect Task Group: Status and
Proposal Overview
Walter,
Thanks! These changes should be fairly easy to make.
- MM
From: ibis-interconn-bounce@xxxxxxxxxxxxx
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Wednesday, January 25, 2017 2:23 PM
To: IBIS-Interconnect <ibis-interconn@xxxxxxxxxxxxx>
Subject: [ibis-interconn] Re: IBIS Interconnect Task Group: Status and
Proposal Overview
MM,
Significant suggestions for Slide 5 and 8
Walter
Slide 5
q Any useful interconnect improvement proposal must support.
- Coupled and uncoupled I/O models
- POWER and GND models
- Coupled I/O and POWER and GND models
- Clear identification of aggressors and victims in coupled sims
- IBIS-ISS and Touchstone models
- Models can be from pin to buffer or can be split into package and
on-die interconnect
- Connections without requiring legacy package keywords
- Explicit identification of interconnect terminals by pin_name,
signal_name or even [Pin Mapping] bus_label
Slide 8 split into two slides
Interconnect Models and Model Sets
Designed to Support the Way Package
and On-Die Interconnect Models are
Generated and Delivered Today
- Identify whether a coupled signal is only an aggressor or also
"experiences" coupling from all other sources
Slide 8a
q Interconnect Model Sets
- Any Grouping Interconnect Models
- Can have separate Interconnect Model Sets for different interfaces
q DDR Memory subsystem
q PCEi Bus
q Power
- Can have separate Interconnect Model Sets for coupled simulations
- Can have separate POWER and GND Interconnect Model Sets
q Simple POWER and GND with each POWER and GND signal names lumped into a
single terminal at the Pins and on the Silicon
q Detailed POWER and GND with a terminal for each POWER and GND pin, and
POWER and GND rail connection at each I/O buffer.
q Middle ground where groups of pins (bus_labels) are connected to a single
terminal.
Walter
From: ibis-interconn-bounce@xxxxxxxxxxxxx
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Mirmak, Michael
Sent: Wednesday, January 25, 2017 4:56 PM
To: IBIS-Interconnect (ibis-interconn@xxxxxxxxxxxxx)
<ibis-interconn@xxxxxxxxxxxxx>
Subject: [ibis-interconn] IBIS Interconnect Task Group: Status and Proposal
Overview
(apologies if you receive this twice)
Please find enclosed an updated presentation, "IBIS Interconnect Task Group:
Status and Proposal Overview" for the IBIS Summit at DesignCon, with changes
from today's task group meeting review. Additional comments and suggestions
are welcome.
- MM
