Minutes from the 16 November 2018 IBIS Editorial Task Group meeting are
attached.
Regards,
Justin
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IBIS EDITORIAL TASK GROUP
http://www.ibis.org/editorial_wip/ ;
Mailing list: ibis-editorial@xxxxxxxxxxxxx
Archives at //www.freelists.org/archive/ibis-editorial/
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Attendees from November 16, 2018 Meeting (* means attended at least using audio)
ANSYS Curtis Clark
Cadence Design Systems Bradley Brim
Intel Corp. Michael Mirmak*
Keysight Technologies Radek Biernacki*
Mentor, A Siemens Business Arpad Muranyi*
Micron Technology Justin Butterfield*, Randy Wolff
SiSoft Walter Katz, Mike LaBonte
Teraspeed Labs Bob Ross*
Michael Mirmak convened the meeting. No patents were declared.
Justin Butterfield took minutes.
Review of minutes from the November 14 meeting:
Radek Biernacki moved to approve. Bob Ross seconded. Minutes were approved
without objection.
Review of ARs:
- Michael to send out the latest draft and checklist.
- Michael reported these were posted, but were not sent out yet.
Opens:
- None.
Editorial review of ver7_0_181114.docx and the task checklist:
Michael stated we have 10 checklist items remaining, and the finalization items
6 and 7 need to be done at the very end. He stated that adding BIRD196.1 to
the list of BIRDs is done. We marked checklist item 84 as verified.
Michael noted checklist item 74 is for the numbering indentation in the Table
of Contents. He asked if the Table of Contents looks okay. Radek replied it
does. Bob asked if there are any line wrapping issues. Michael replied there
are no line wraps in the Table of Contents. Arpad Muranyi asked if there is a
way to reduce the amount of space between the section numbers and the titles.
Radek thought this looks okay as is. Bob commented we are limited by the
deeper section numbers such as 6.3.1. Michael stated this can be done to make
the titles and numbers closer. Bob stated we should make the numbers and
titles for sections of the same level aligned and be careful between numbers 9
and 10 which require an extra space.
Michael commented the table widths, page breaks and vertical spacing in the
document needs to be reviewed, but this can be done towards the end.
Michael stated we have a checklist item on the line wrapping in the Table of
Tables and Table of Figures. Radek asked about the title for Figure 25 where
VHDL-A(MS) line wraps after the dash. Bob suggested to change the title moving
the word "Example" to the end of title. Arpad asked if we can remove the word
"Example" from the title. Bob thought this would be okay, since it is not a
syntax example. Arpad stated we should also look at the other figure captions
to remove the word "Example". Michael changed Figures 26 and 27 to change the
word "Example" to "Illustration". He also simplified the title for Figure 29.
After some further discussion, Michael changed "Illustration" to "I/O Buffers"
for Figures 25, 26, 27 and 29. Bob commented we do not show the distinction
between I/O, Input and Output buffers in these figures. Arpad suggested to say
"Pseudo-Differential Buffer" for Figure 26. Michael suggested to say
"Multi-lingual" rather than "SPICE, Verilog-AMS, VHDL-AMS" in these figure
captions. Radek suggested to change the Figure 27 title to "Multi-lingual
*-AMS I/O Buffers".
Michael stated we have line wrap issues in the Table of Tables. Bob was also
concerned that some of the tables are very similarly named. Michael stated
that some of the tables have slightly difference names, but the table names are
accurate and consistent. Bob noted there is one set of duplicate tables.
Michael agreed this is expected noting that Table 17 and Table 43 are
intentionally duplicates. Arpad asked if we can reduce the names for some of
the tables. Michael stated that we have symmetry with the other table names,
and we would have to change them all to be consistent. Arpad suggested to
change "general rules and allowable usage" to "general rules". Bob thought it
would be better to say "allowable usage". Michael noted we have columns
labeled "general rules" and "allowable usage" in these tables. Radek thought
these table captions are okay as is.
Arpad stated Table 6 and Table 7 names are rather long. He suggested to remove
the parenthetical from the captions. Bob stated this is a critical part of
this feature. Michael suggested to add the text from the parenthetical as a
note. Arpad agreed with this. Michael also noted the term "Vdie" is not
defined anywhere but is used in the tables. He suggested to add a
parenthetical on page 102 after the phrase "starting voltage". Arpad asked if
the die voltage is the buffer pad voltage and suggested to say "buffer pad die
voltage". Michael agreed with this. We marked checklist item 87 as verified.
Michael stated we need to cleanup "GND" vs. "Gnd".
We agreed to meet on Wednesday next week.
Michael will send out the latest draft and checklist [AR].
Arpad moved to adjourn. Radek seconded. The meeting adjourned without
objection.
The next meeting will take place Wednesday, November 21, at 8 AM Pacific.
Open Technical Questions:
1. BIRD182: POWER and GND [Pin] signal_name as [Pin Mapping] bus_label
a. Is a bus_label created even if we don't have [Pin Mapping], [Bus Label],
or [Die Supply Pads] through the [Pin]?
b. Is a bus_label short created for legacy package models based on the
second column of [Pin] when we do not have a [Pin Mapping] entry?
