[SI-LIST] Re: negative propagation delay
- From: "Ingraham, Andrew" <a.ingraham@xxxxxxxx>
- To: <perry.qu@xxxxxxxxxxx>
- Date: Fri, 3 Oct 2003 10:57:37 -0400
> As a few people pointed out to me offline, negative delay should be ok as
> it
> reflected the situation that Tco for my real load should be smaller since
> my
> real load is smaller.
And it's not really negative delay. It's just one number that is smaller
than another number. So if you express the first number with respect
to the second number as your reference, then the first number would
be negative.
It's like driving a car at 90 km/h and noticing that the car next to you,
which is going only 80 km/h, seems to be driving backwards. The faster
you go, the more he seems to be going backwards.
But (total) delay is always positive. The car next to you still gets to the
exit ramp after the entrance ramp.
> I guess the only
> reason I need to watch out negative delay is for hold time margin, since
> if
> I plugged in a negative delay for Hold time margin calculation, I may end
> up
> with negative margin.
I don't follow this. If the delays are such that your value for "wire"
delay (or whatever you or your tool calls it) is negative, then that's
what it is. Yes, Hold time problems do happen, they can happen
whether the propagation delay number is positive, negative, or zero.
Having a negative delay number does not necessarily mean there is
a Hold time violation.
You should never "correct" or modify a propagation delay number
just because it's negative.
The reason this stuff happens, is that the delay of a driver part is not
independent on the load you connect to it. You can't separate out the
delay of the driver alone, from the delay of the interconnect/load. So
the approach we take, is to measure and specify the delay of the driver
with some sort of "standard" or "test" load attached.
A load of zero (0pF) might be better than 50pF from the point of view
of partitioning the part's internal delay from the load's effect on delay,
except that 0pF loads are impractical to use, and ultimately everything
on the part's data sheet needs to be tested on an IC tester with realizable
loads. The data sheet generally reflects what is testable.
Also, there are people who do back-of-envelope timing analysis without
simulating their interconnects, and it's better to use a test load that is
similar to the actual load one might typically attach to a part, so that the
customer doesn't get unrealistic expectations.
Regards,
Andy
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