[SI-LIST] Re: negative propagation delay

  • From: "Douglas Burns" <dburns@xxxxxxxxxx>
  • To: <perry.qu@xxxxxxxxxxx>, "si-list" <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 2 Oct 2003 15:23:47 -0400

Perry,

 The IBIS reference load is supposed to represent the standard load into
which the componet is tested and it's AC spec's generated from. Simulate the
driver into the reference load and then simulate the driver into your load.
You will get two delay values; Tref and Tactual. What you will notice is
that the value Tref will not equal the Spec AC Tco of your device. This is
because the IBIS model does not model the delay thru the device, only it's
IO characteristics (In most cases, the SPICE models also do not model the
full output path delay). By subtracting Tref from Tactual, you will obtain
the interconnect delay with respect to the reference load Twire =
(Tactual -Tref).

So now you have 2 pieces of data:
        1) Delay of device into standard load (Tco)
        2) Interconnect delay with respect to standard load (Twire)

 To compute your timing delay, add the Twire value to the spec Tco of your
device.


Douglas Burns
Chief Consultant
Signal Integrity Software Inc.
6 Clock Tower Place
Maynard, MA 01754
978-461-0449 x14
www.sisoft.com
dburns@xxxxxxxxxx




-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Perry Qu
Sent: Thursday, October 02, 2003 3:03 PM
To: si-list
Subject: [SI-LIST] negative propagation delay


Hi,

I'm using ICX for SI/timing analysis. One thing I noticed, if a driver
IBIS specified a large reference load (e.g., 50pF for uP), I will always
end up with a negative propagation delay since my actual loading is much
smaller compared with reference load.

Would like to understand how I should correct the number to reflect my
actual loading for timing analysis. I would think we can get the
internal logic delay of driver through: (Tco - time_to_Vmeas@reference
load); But then, how shall I add buffer delay for a real load and
propagation delay for a real load--taking into account all the
reflection effect (e.g., a daisy-chained bi-directional data bus).

Thanks

Perry

--
Perry Qu

Design & Qualification       |      600 March Road
Alcatel Canada               |      Ottawa, ON K2K 2E6, Canada

DID: (613) 7846720           |      FAX: (613) 5993642


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