[SI-LIST] Re: diffusion capacitance measurement
- From: Yafei Bi <yafei_bi@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 14 Jul 2004 22:45:47 -0700 (PDT)
From orginal post, it's not clear to me what the
purpose of the exercise is. for a rough calculation to
figure something out, Cj, CJSW as well the simulation
may or may not be adequate.
However, I do agree the models for these capacitance
provided by foundry often don't match silicon.
To figure out Cj, CJSW and overlap cap separately, you
can measure CGD, CGS, CDB, CSB, etc. based on the
relationship of these capacitance under different bias
condition, individual component can be extracted.
Best regards,
Yafei
--- Raymond.Leung@xxxxxxxxxxx wrote:
>
>
>
> The first suggestion goes back to my previous claim
> that the
> hand-calculated Cj and Cjsw is not accurate since:
>
> 1) you don't know the doping profiles,
> 2) you don't know the equivalent junction depth,
> 3) you don't know the doping density, and
> 4) other channel implants may affect the effective
> doping profiles.
>
> Even if you can find the overall capcitance of the
> node, how
> can you tell the portions from Cj, Cjsw and overlap
> cap
> from the drain to the gate?
>
> Regards,
> Raymond
>
>
>
>
>
> Yafei Bi <yafei_bi@xxxxxxxxx> on 15/07/2004 14:09:03
>
> Please respond to yafei_bi@xxxxxxxxx
>
> To: Raymond Leung/sdc@sdc, si-list@xxxxxxxxxxxxx
> cc:
>
> Subject: [SI-LIST] Re: diffusion capacitance
> measurement
>
>
>
> Ashvin,
>
> Sounds like you already have the transistor model
> files, so this is how I would do:
>
> 1). for a hand calculation, look at Hspice model
> file
> for MOS parameter CJ and CJSW, those are bottom
> plate
> and sidewall capacitance.
>
> 2). for a simulation, apply an AC voltage source at
> the nodes(e.g.: drain/source), run .ac simulation,
> probe the ac current goes into the nodes. the
> impedance of nodes can be calaculated as:
> R=V/I, I is your ac current.
> impedance R=1/(2*pi*f*c).
>
> you know the frequceny at which the current is
> measured, so: c = I/(2*pi*f*V).
>
> you can verify whether the simulation results
> matches
> the hand calculation.
>
> Alternatively, I agree with Raymond, just ask your
> foundary, their documentation should have these
> number
> readily.
>
> Regards,
>
> Yafei
>
> --- Raymond.Leung@xxxxxxxxxxx wrote:
> >
> >
> > Ashvin,
> >
> > You cannot calculate the area/perimeter diffusion
> > capacitances
> > accurately because they are very process
> dependent.
> > There is a way
> > to measure them out from the test devices which
> are
> > specially
> > designed for this purpose, but I don't think the
> > faundry will let you
> > do it yourself. Perhaps the best way is to ask
> your
> > faundry for the
> > figures.
> >
> > Regards,
> > Raymond
> >
> >
> >
> >
> >
> > "ashvin khole" <ashvinkhole@xxxxxxxxxxx> on
> > 14/07/2004 22:51:23
> >
> > Please respond to ashvinkhole@xxxxxxxxxxx
> >
> > To: si-list@xxxxxxxxxxxxx
> > cc: (bcc: Raymond Leung/sdc)
> >
> > Subject: [SI-LIST] diffusion capacitance
> > measurement
> >
> >
> >
> > Hi Can someone guide me to the appropriate way to
> > measure area and
> > perimeterdiffusion capacitance for a transistor
> > model both by simulation and
> > hand calculation? I have the appropriate model
> files
> > for the transistor
> > model. Thanks Ashvin
> >
>
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> >
> >
> >
> >
> >
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