[SI-LIST] Re: Waveform edge ringing
- From: "Nijagunamurthy, Hithesh (GE Intelligent Platforms)" <hithesh@xxxxxx>
- To: "Andrew Ingraham" <a.ingraham@xxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 9 Dec 2010 22:49:47 +0530
Andrew,
Yes, the clocks are not daisy chained. They are routed individually.
No SI issues there.
When I saw the waveforms with non-monotonic edge, I panicked for a while. But
then when you think about it, they are ok if they are data/addr lines.
-Hithesh
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx on behalf of Andrew Ingraham
Sent: Thu 12/9/2010 2:47 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Waveform edge ringing
(I don't know why I am only now receiving this thread, but I am.)
Hithesh,
Hopefully your clocks are not daisy-chained. If they are, that is a mistake.
PCI clocks are edge-triggered and do not tolerate plateaus or ringing.
Non-monotonic clock waveforms are bad. It doesn't matter if the
waveform crosses Vih (or Vil) once or twice. If it is non-monotonic
anywhere that includes the region between Vil and Vih, it could be
bad. If the receiver sees the glitch/ringing and passes it on to the
internal clock circuitry, you're screwed.
Be aware that waveforms at IC pins may be slightly worse than those
than those the receiver actually sees.
Address and data signals are effectively sampled only at the clock
edges (+/- setup time and hold time) and ignored the rest of the time.
They generally do look like your waveform, or worse, and it doesn't
matter AS LONG AS ultimately the timing is satisfied.
As a first order, look at when each rising signal first hits Vil and
when it last crosses Vih, and vice-versa when falling, and check those
against your timing requirements (which MUST be known). How the
signals behave between the time they first enter Vil/Vih, and last
leave Vil/Vih, is pretty much unimportant; they can wiggle all over
the place. For the address and data signals, that is.
How much time a signal spends above Vih before ringing back below Vih
is unimportant.
You do need to know your parts' setup and hold times
Regards,
Andy
> I am doing signal integrity simulation for PCI Address/Data bus signals
> going from an FPGA to a Power PC.
> The signals are daisy chained from the FPGA to 6 Power PCs. The daisy
> chain routing is 55 ohm impedance controlled.
...
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