[SI-LIST] Re: Waveform edge ringing
- From: Alfred Lee <alfred1520list@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 16 Dec 2010 20:17:29 -0800
>the voltage at the
>load will be 2x the line voltage. So, no problems at the load. But the
>chips sitting along the line, will see half Vcc and then full Vcc after
>a while.
The last time I get to read the SPI spec. was a long time ago, but my
recollection is that the PCI is neither source nor end terminated, hence for a
low impedance source the initial line voltage could be close to VCC. The
reflected voltage could be doubled of that. Hence for the original 5V PCI
compatible devices they must tolerate +11V/-5.5V of over/undershoot. Something
to consider for non PCI specific devices in term of over/undershoot / long term
reliability issues.
Regards,
Alfred
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