[SI-LIST] Waveform edge ringing
- From: "Nijagunamurthy, Hithesh (GE Intelligent Platforms)" <hithesh@xxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 23 Nov 2010 16:23:32 +0530
I am doing signal integrity simulation for PCI Address/Data bus signals
going from an FPGA to a Power PC.
The signals are daisy chained from the FPGA to 6 Power PCs. The daisy
chain routing is 55 ohm impedance controlled.
The waveform edge has some ringing at VIH on the rising edge and VIL at
the falling edge. The ringing is only for one cycle(see pic).
Can this be counted as a valid waveform.
Let's say this is input to a clock buffer.
The part where I am confused is(on the rising edge) the waveform goes
above VIH, so now the output of the receiver IC should be High. Now if
the edge goes 200mV below VIH after say 1ns, and comes back to Vcc, will
the output of the receiver change?
There is similar behavior at VIL.
Now, let's say this is Addr or data line. Would the setup time would be
violated?
Image - http://www.imgplace.com/viewimg217/6307/69wave.jpg
Thanks.
-Hithesh
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
