[SI-LIST] Re: Waveform edge ringing
- From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 07 Dec 2010 08:04:14 +0100
Hello,
the original PCI is a very "dirty" bus. It uses a concept called
reflected wave switching
(http://en.wikipedia.org/wiki/Reflected-wave_switching)
So there is no termination on the end, and the Address data signals rely
on getting the reflected wave to achive the correct swing.
==> on Address and datalines it is normal to see this kind of reflection
(in the middle of the bus .. as Eddy mentioned, at the end it should
look better).
To ensure the setup time is not violated I think to remember that PCI
defined the maximum Roundtrip to 10ns.
On the clock I would need to re-check the spec. I would expect a problem
with this kind of waveform.
But I think to remember seperate PCI-Clocks should be routed to each PCI
target device ?!? Sorry, this it's some time ago that I have worked with
PCI ...
Best regards
Hermann
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
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94554 Moos
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schrieb Eddy:
> This looks like the waveform on an input somewhere halfway the daisy chain.
> When you match a CMOS driver to a trace with a series resistor and then leave
> the trace open at the very end, this is only good when you have just one
> input at the very end of that trace. Halfway the trace you will see
> reflections like the "ringing" as you call it halfway low and high levels.
> The only way to get rid of the reflections is to properly terminate the end
> of the trace but that will be difficult to do with CMOS levels.
> Perhaps you can filter the signal where you are tapping off the trace
> somewhere halfway. A ferrite bead in series with the signal might "choke" the
> high frequency ring enough so it becomes monotonic rising at the target input.
> Eddy van Keulen
> Sr. FAE Mgr., PhaseLink Corp.
> KF6PLO
>
>
> --- On Tue, 11/23/10, Nijagunamurthy, Hithesh (GE Intelligent Platforms)
> <hithesh@xxxxxx> wrote:
>
> From: Nijagunamurthy, Hithesh (GE Intelligent Platforms) <hithesh@xxxxxx>
> Subject: [SI-LIST] Waveform edge ringing
> To: si-list@xxxxxxxxxxxxx
> Date: Tuesday, November 23, 2010, 2:53 AM
>
> I am doing signal integrity simulation for PCI Address/Data bus signals
> going from an FPGA to a Power PC.
> The signals are daisy chained from the FPGA to 6 Power PCs. The daisy
> chain routing is 55 ohm impedance controlled.
>
> The waveform edge has some ringing at VIH on the rising edge and VIL at
> the falling edge. The ringing is only for one cycle(see pic).
> Can this be counted as a valid waveform.
> Let's say this is input to a clock buffer.
> The part where I am confused is(on the rising edge) the waveform goes
> above VIH, so now the output of the receiver IC should be High. Now if
> the edge goes 200mV below VIH after say 1ns, and comes back to Vcc, will
> the output of the receiver change?
> There is similar behavior at VIL.
>
> Now, let's say this is Addr or data line. Would the setup time would be
> violated?
>
> Image - http://www.imgplace.com/viewimg217/6307/69wave.jpg
>
> Thanks.
> -Hithesh
>
>
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