[SI-LIST] Re: Variable Freq generator for Circuit/Schematic Testbenching

  • From: "Taha Amiralli" <thamiral@xxxxxxxxx>
  • To: "George Opsahl" <g_opsahl@xxxxxxxxx>
  • Date: Wed, 13 Dec 2006 22:07:46 -0500

Thanks for your interest in the problem George,
I have heard of psuedo random counters before, but unfortunately, I dont see
how they would be used to generate an element that yields a simulation time
programmable frequency for use in a test bench. I'd appreciate it if you
could elaborate a bit more on this...

Thanks,

Sincerely,

-------------------
Taha Amiralli
thamiral [A] uwo [D] ca
thamiral [A] gmail [D] com

MESc Candidate 2007, Computer Engineering
The University Of Western Ontario

BESc, BSc. 2005,
Computer Engineering & Computer Science
The University Of Western Ontario
---------------------------------------------------------------



On 12/13/06, George Opsahl <g_opsahl@xxxxxxxxx> wrote:
>
>
> You might want to try a psuedo random counter.
>
> Sincerely,
> George Opsahl
> Web Site:  http://ibismodels.tripod.com
> Email:  ibismodels@xxxxxxxxx
>
>
>
> --- Taha Amiralli <thamiral@xxxxxxxxx> wrote:
>
> > Dear all,
> > Does anyone have any ideas on the best way of creating a
> > variable/run-time-Programmable frequency clock/source for test
> > benching
> > mixed signal circuits/schematics using the spectre circuit simulator?
> >
> > I have tried a number of temporary solutions such as writing a
> > frequency
> > divider using verilogA that counts edges in a Vpulse signal or trying
> > to use
> > the timer events in verilogA or even using an analog mux and a series
> > of
> > input frequencies. However, all these methods are not flexible and
> > they only
> > work for pulses.
> >
> > Any elegant solutions/suggestions for this problem would really be
> > appreciated. I'd prefer not to have to create a PLL in a CSU mode ...
> >  :)
> >
> > Thanks,
> >
> > Sincerely,
> >
> > -------------------
> > Taha Amiralli
> > thamiral [A] uwo [D] ca
> > thamiral [A] gmail [D] com
> >
> > MESc Candidate 2007, Computer Engineering
> > The University Of Western Ontario
> >
> > BESc, BSc. 2005,
> > Computer Engineering & Computer Science
> > The University Of Western Ontario
> > ---------------------------------------------------------------
> >
> >
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