[SI-LIST] Re: Variable Freq generator for Circuit/Schematic Testbenching
- From: "Kenneth W. Egan" <kegan@xxxxxxxxxxxxx>
- To: <thamiral@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 13 Dec 2006 23:06:50 -0600
Why not create a behavioral VCO in spice using an 'E' element. If you truly
want a random frequency, you can create a behavioral LFSR
( linear feedback shift register) whose outputs drive a DAC implmented via a
R2R ladder network. This, drives the control voltage to the VCO. The LFSR
clock can be a standard spice 'PULSE' function to control the update rate of
the VCO.
Range of the VCO is totally controlled by the 'E' element setup as well as
the range of the R2R DAC implementation.
KWE
>
>
>
> --- Taha Amiralli <thamiral@xxxxxxxxx> wrote:
>
> > Dear all,
> > Does anyone have any ideas on the best way of creating a
> > variable/run-time-Programmable frequency clock/source for test
> > benching mixed signal circuits/schematics using the spectre circuit
> > simulator?
> >
> > I have tried a number of temporary solutions such as writing a
> > frequency divider using verilogA that counts edges in a Vpulse
> > signal or trying to use the timer events in verilogA or even using
> > an analog mux and a series of input frequencies. However, all these
> > methods are not flexible and they only work for pulses.
> >
> > Any elegant solutions/suggestions for this problem would really be
> > appreciated. I'd prefer not to have to create a PLL in a CSU mode ...
> > :)
> >
> > Thanks,
> >
> > Sincerely,
> >
> > -------------------
> > Taha Amiralli
> > thamiral [A] uwo [D] ca
> > thamiral [A] gmail [D] com
> >
> > MESc Candidate 2007, Computer Engineering The University Of Western
> > Ontario
> >
> > BESc, BSc. 2005,
> > Computer Engineering & Computer Science The University Of Western
> > Ontario
> > ---------------------------------------------------------------
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