[SI-LIST] Re: Variable Freq generator for Circuit/Schematic Testbenching
- From: "Taha Amiralli" <thamiral@xxxxxxxxx>
- To: "Kenneth W. Egan" <kegan@xxxxxxxxxxxxx>, si-list <si-list@xxxxxxxxxxxxx>
- Date: Thu, 14 Dec 2006 13:09:34 -0500
Thats a good suggestion Kenneth. In fact, I have used VCVS before to model
VCOs by setting the output voltage to a sine wave who's frequency is
dependent on the input voltage of the VCVS element.
If however, I needed to generate a clock or square pulses, how would one go
about writing a SquareWave function that outputs either 1 or 0 given only
the mathematical/behavioral functions that spectre provides? For now, I am
using a user defined SquareWave function in verilogA to generate a square
wave based on an input frequency, however, it would be nice to have a more
elegant way of doing this.
I would think this is a common operation and thus, I was hoping that spectre
might have some inbuilt functionality that can be used for this kind of
behavioral modeling.
Thanks for the interest in the problem...
Sincerely,
-------------------
Taha Amiralli
thamiral [A] uwo [D] ca
thamiral [A] gmail [D] com
MESc Candidate 2007, Computer Engineering
The University Of Western Ontario
BESc, BSc. 2005,
Computer Engineering & Computer Science
The University Of Western Ontario
---------------------------------------------------------------
On 12/14/06, Kenneth W. Egan <kegan@xxxxxxxxxxxxx> wrote:
>
> Why not create a behavioral VCO in spice using an 'E' element. If you
> truly
> want a random frequency, you can create a behavioral LFSR
> ( linear feedback shift register) whose outputs drive a DAC implmented via
> a
> R2R ladder network. This, drives the control voltage to the VCO. The LFSR
> clock can be a standard spice 'PULSE' function to control the update rate
> of
> the VCO.
>
> Range of the VCO is totally controlled by the 'E' element setup as well as
> the range of the R2R DAC implementation.
>
> KWE
>
> >
> >
> >
> > --- Taha Amiralli <thamiral@xxxxxxxxx> wrote:
> >
> > > Dear all,
> > > Does anyone have any ideas on the best way of creating a
> > > variable/run-time-Programmable frequency clock/source for test
> > > benching mixed signal circuits/schematics using the spectre circuit
> > > simulator?
> > >
> > > I have tried a number of temporary solutions such as writing a
> > > frequency divider using verilogA that counts edges in a Vpulse
> > > signal or trying to use the timer events in verilogA or even using
> > > an analog mux and a series of input frequencies. However, all these
> > > methods are not flexible and they only work for pulses.
> > >
> > > Any elegant solutions/suggestions for this problem would really be
> > > appreciated. I'd prefer not to have to create a PLL in a CSU mode ...
> > > :)
> > >
> > > Thanks,
> > >
> > > Sincerely,
> > >
> > > -------------------
> > > Taha Amiralli
> > > thamiral [A] uwo [D] ca
> > > thamiral [A] gmail [D] com
> > >
> > > MESc Candidate 2007, Computer Engineering The University Of Western
> > > Ontario
> > >
> > > BESc, BSc. 2005,
> > > Computer Engineering & Computer Science The University Of Western
> > > Ontario
> > > ---------------------------------------------------------------
> > >
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