[SI-LIST] Re: Stub length of a clock

I agree with James and would like to add that another possibility lies in
splitting the termination for a T'd signal.
e.g. from source to `T' with Zo impedance
From `T' to both receivers with 2 x Zo impedance.
terminating at the receivers with 2 x Zo resistance.

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James_R_Jones@xxxxxxxx wrote:

> The basic relation is that a shelf will occur at half signal swing at the
> receiver that is approx 2 times the time of flight of the stub.  This shelf
> may introduce unacceptable timing uncertainty.  You could fix this problem
> by routing two traces from the driver to each of the loads.  Use a series
> terminator for each line at the source and you should probably simulate to
> determine the R values.  Beware that this approach is doubly loading the
> clock driver, which may or may not have adequate drive strength to keep
> adequate edge rate.
>
> You could also terminate at the teed topology at the receivers to get rid of
> the shelf, and once again I would probably simulate in order catch all of
> the problems with this.
>
> Hope this helps,
> James R. Jones
>
> -----Original Message-----
> From: Hora Abu [mailto:arageeb@xxxxxxxxx]
> Sent: Thursday, January 23, 2003 5:58 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Stub length of a clock
>
> Dear SI expert,
>
> I have two loads that I need to support with one clock. I route the clock
> from the generator to half way between the loads and T off to stubs each
> going to its target load. I know that the stub needs to be minimize but I
> can only make so short. Transmission line theory suggest there is a
> relationship between the stub length and signal rise time? does any know
> this relation or can point me to an article.
>
> Thanks
>
> Hura
>
> arag abu deeb
>
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