Posts for si-list, 01-2003

Browse: Last Month: 12-2002 Main Archive Page Next Month: 02-2003

» [SI-LIST] Signal Integrity Engineer Available -
» [SI-LIST] test -
» [SI-LIST] Re: output circuit for 68000 NMOS driver -
» [SI-LIST] SI engineer seeking employment -
» [SI-LIST] Re: Matching impedance -
» [SI-LIST] Re: Different Spice netlists -
» [SI-LIST] Re: Matching impedance -
» [SI-LIST] Re: Different Spice netlists -
» [SI-LIST] Conductor Ampacity question -
» [SI-LIST] Re: Different Spice netlists -
» [SI-LIST] RMCEMC Bonus Feb Meeting Reminder -
» [SI-LIST] Re: Different Spice netlists -
» [SI-LIST] Re: How accurate is HSPICE's field solver? -
» [SI-LIST] Re: Matching impedance -
» [SI-LIST] Re: How accurate is HSPICE's field solver? -
» [SI-LIST] Re: Different Spice netlists -
» [SI-LIST] output circuit for 68000 NMOS driver -
» [SI-LIST] Re: Different Spice netlists -
» [SI-LIST] Re: How accurate is HSPICE's field solver? -
» [SI-LIST] How accurate is HSPICE's field solver? -
» [SI-LIST] Re: Different Spice netlists -
» [SI-LIST] Re: IBIS Models -
» [SI-LIST] Re: Different Spice netlists -
» [SI-LIST] Matching impedance -
» [SI-LIST] Re: EMI fixed by flooding? -
» [SI-LIST] Re: impedance matching for high freq PCB -
» [SI-LIST] EMI fixed by flooding? -
» [SI-LIST] Re: Need help for VCO simulation. -
» [SI-LIST] Need help for VCO simulation. -
» [SI-LIST] Re: High-Speed GHz differential signals routed Broadside Coupled -
» [SI-LIST] Re: High-Speed GHz differential signals routed Broadside Coupled -
» [SI-LIST] Re: Capacitors UNDER a BGA?? -
» [SI-LIST] XFP Serial Interface Article (FYI) -
» [SI-LIST] New Hardware Job Interview Question -
» [SI-LIST] Re: junior designer question -
» [SI-LIST] junior designer question -
» [SI-LIST] Inverter/buffer -
» [SI-LIST] Re: High-Speed GHz differential signals routed Broadside Coupled -
» [SI-LIST] Re: Question on IBIS: rising/falling waveform - How complete waveform created? -
» [SI-LIST] Re: Capacitors UNDER a BGA?? -
» [SI-LIST] impedance matching for high freq PCB -
» [SI-LIST] Re: Capacitors UNDER a BGA?? -
» [SI-LIST] Capacitors UNDER a BGA?? -
» [SI-LIST] Re: Question on IBIS: rising/falling waveform - How complete waveform created? -
» [SI-LIST] Re: Source termination of LVDS drivers -
» [SI-LIST] Re: Source termination of LVDS drivers -
» [SI-LIST] Re: CMI encoded signal -
» [SI-LIST] CMI encoded signal -
» [SI-LIST] Autogerb questions -
» [SI-LIST] Re: HFSS solution issue -
» [SI-LIST] SPI 2003 1st announcement -
» [SI-LIST] Different Spice netlists -
» [SI-LIST] Re: IBIS & the Simulator -
» [SI-LIST] Re: Interference from planar magnetics -
» [SI-LIST] Re: IBIS & the Simulator -
» [SI-LIST] Re: IBIS & the Simulator -
» [SI-LIST] Re: IBIS & the Simulator -
» [SI-LIST] Re: [OFF TOPIC] SMD Land patterns -
» [SI-LIST] Re: HFSS solution issue -
» [SI-LIST] Re: Interference from planar magnetics -
» [SI-LIST] Re: Interference from planar magnetics -
» [SI-LIST] Re: [OFF TOPIC] SMD Land patterns -
» [SI-LIST] Re: [IS-LIST] Source termination of LVDS drivers -
» [SI-LIST] Source termination of LVDS drivers -
» [SI-LIST] R: [OFF TOPIC] SMD Land patterns -
» [SI-LIST] [OFF TOPIC] SMD Land patterns -
» [SI-LIST] Re: Interference from planar magnetics -
» [SI-LIST] Re: Interference from planar magnetics -
» [SI-LIST] Re: How calculate the capacitance between via and plane -
» [SI-LIST] IBIS & the Simulator -
» [SI-LIST] Re: SPICE Model for Common Mode Choke -
» [SI-LIST] test-please ignore -
» [SI-LIST] fields question -
» [SI-LIST] Re: Question on IBIS: rising/falling waveform - How complete waveform created? -
» [SI-LIST] HOW Hspice is Useful in SI analysis for PCB designs?? -
» [SI-LIST] Re: How calculate the capacitance between via and plane -
» [SI-LIST] Re: How calculate the capacitance between via and plane -
» [SI-LIST] Re: SPICE Model for Common Mode Choke -
» [SI-LIST] How calculate the capacitance between via and plane -
» [SI-LIST] Re: SPICE Model for Common Mode Choke -
» [SI-LIST] Re: Interference from planar magnetics -
» [SI-LIST] SPICE Model for Common Mode Choke -
» [SI-LIST] Interference from planar magnetics -
» [SI-LIST] FWD: Re: Re: HFSS solution issue -
» [SI-LIST] Re: Stub length of a clock -
» [SI-LIST] Re: Model generation -
» [SI-LIST] Re: over & under shoots -
» [SI-LIST] Re: Question on IBIS: rising/falling waveform - H ow complete waveform created? -
» [SI-LIST] Steve Wood/TOSHIBA_TEE is out of the office. -
» [SI-LIST] Re: HFSS solution issue -
» [SI-LIST] Re: HFSS solution issue -
» [SI-LIST] Re: HFSS solution issue -
» [SI-LIST] Re: Question on IBIS: rising/falling waveform - How complete waveform created? -
» [SI-LIST] Re: Question on IBIS: rising/falling waveform - How complete waveform created? -
» [SI-LIST] Re: Stub length of a clock -
» [SI-LIST] Stub length of a clock -
» [SI-LIST] Re: Cosmoscope for eye-diagrams ?? -
» [SI-LIST] Cosmoscope for eye-diagrams ?? -
» [SI-LIST] Re: Model generation -
» [SI-LIST] Model generation -
» [SI-LIST] Re: over & under shoots -
» [SI-LIST] Re: question on IBIS: rising/falling waveform. -
» [SI-LIST] Re: question on IBIS: rising/falling waveform. -
» [SI-LIST] Re: HFSS solution issue -
» [SI-LIST] Re: Question on IBIS: rising/falling waveform - How complete waveform created? -
» [SI-LIST] HFSS solution issue -
» [SI-LIST] Re: over & under shoots -
» [SI-LIST] Re: over & under shoots -
» [SI-LIST] Re: FWD: RE: Some issues related to spiral inductor modelling. -
» [SI-LIST] Re: FWD: RE: Some issues related to spiral inductor modelling. -
» [SI-LIST] Re: FWD: RE: Some issues related to spiral inductor modelling. -
» [SI-LIST] Re: Some issues related to spiral inductor modelling. -
» [SI-LIST] over & under shoots -
» [SI-LIST] help me guys -
» [SI-LIST] Re: FWD: RE: Some issues related to spiral inductor modelling. -
» [SI-LIST] Re: question on IBIS: rising/falling waveform. -
» [SI-LIST] question on IBIS: rising/falling waveform. -
» [SI-LIST] How complete waveform created? -
» [SI-LIST] Re: FWD: PCB Trace Z, C, & L relationship -
» [SI-LIST] Re: FWD: PCB Trace Z, C, & L relationship -
» [SI-LIST] Re: FWD: PCB Trace Z, C, & L relationship -
» [SI-LIST] Re: FWD: PCB Trace Z, C, & L relationship -
» [SI-LIST] Re: FWD: RE: Some issues related to spiral inductor modelling. -
» [SI-LIST] Re: FWD: Beylium Copper -
» [SI-LIST] Re: FWD: Beylium Copper -
» [SI-LIST] Re: Berrylium Copper -
» [SI-LIST] Re: FWD: Berylium Copper -
» [SI-LIST] FWD: RE: Some issues related to spiral inductor modelling. -
» [SI-LIST] FWD: Re:_[SI-LIST]the placement of bypass/decoupling capacitors -
» [SI-LIST] FWD: Beylium Copper -
» [SI-LIST] FWD: Routing Differential PECL Signals -
» [SI-LIST] FWD: PCB Trace Z, C, & L relationship -
» [SI-LIST] FWD: Re: Ethernet Magnetic Jacks -
» [SI-LIST] FWD: PCD Magazine -
» [SI-LIST] FWD: SI Engineer Job Opening at Stratus in Maynard, MA -
» [SI-LIST] si-list still experiencing moderation problems -
» [SI-LIST] Is-there a Mathcad model available? -
» [SI-LIST] Some issues related to spiral inductor modelling. -
» [SI-LIST] Re: ´ð¸´: Re: [SI-LIST]the palceme nt of bypass/decoupling capacitors -
» [SI-LIST] Re: Spice-models -
» [SI-LIST] Re: ´ð¸´: Re: [SI-LIST]the palcement of bypass/decoupling capacitors -
» [SI-LIST] Re: Spice-models -
» [SI-LIST] Spice-models -
» [SI-LIST] ´ð¸´: Re: [SI-LIST]the palcement of bypass/decoupling capacitors -
» [SI-LIST] Re: De-coupling capacitor -
» [SI-LIST] if any body know abt any seminars in india(Bangalore) -
» [SI-LIST] RMCEMC Bonus February meeting -
» [SI-LIST] Re: Simulationsof a connector -
» [SI-LIST] Re: (no subject) - full summary -
» [SI-LIST] Re: De-coupling capacitor -
» [SI-LIST] Re: De-coupling capacitor -
» [SI-LIST] Re: De-coupling capacitor -
» [SI-LIST] Re: De-coupling capacitor -
» [SI-LIST] Re: De-coupling capacitor -
» [SI-LIST] Re: De-coupling capacitor -
» [SI-LIST] Re: De-coupling capacitor -
» [SI-LIST] Re: Simulationsof a connector -
» [SI-LIST] Re: Simulationsof a connector -
» [SI-LIST] Re: [SI-LIST]the palcement of bypass/decoupling capacitors -
» [SI-LIST] Re: De-coupling capacitor -
» [SI-LIST] Re: De-coupling capacitor -
» [SI-LIST] Re: De-coupling capacitor -
» [SI-LIST] Re: De-coupling capacitor -
» [SI-LIST] Re: De-coupling capacitor -
» [SI-LIST] Re: Combining DC and TRANS analysis -
» [SI-LIST] Re: De-coupling capacitor -
» [SI-LIST] De-coupling capacitor -
» [SI-LIST] Re: Simulationsof a connector -
» [SI-LIST] Re: Simulationsof a connector -
» [SI-LIST] Re: Combining DC and TRANS analysis -
» [SI-LIST] Simulationsof a connector -
» [SI-LIST] Re: Coplanar differential signals -
» [SI-LIST] Re: Coplanar differential signals -
» [SI-LIST] Re: Coplanar differential signals -
» [SI-LIST] Coplanar differential signals -
» [SI-LIST] Seminar on Embedded Passives -
» [SI-LIST] Re: Combining DC and TRANS analysis -
» [SI-LIST] Re: Combining DC and TRANS analysis -
» [SI-LIST] Re: Combining DC and TRANS analysis -
» [SI-LIST] Re: Combining DC and TRANS analysis -
» [SI-LIST] RMCEMC January Meeting reminder -
» [SI-LIST] Re: Flight time skew due to Dk varation -
» [SI-LIST] Combining DC and TRANS analysis -
» [SI-LIST] please provide me ibis model of HCPL 6651 ASAP -
» [SI-LIST] HELP -
» [SI-LIST] Re: [SI-LIST]the palcement of bypass/decoupling capacitors -
» [SI-LIST] Any body have gscan & tkdiff on solaris -
» [SI-LIST] Re: [SI-LIST]the palcement of bypass/decoupling capacitors -
» [SI-LIST] Re: Ethernet Magnetic Jacks -
» [SI-LIST] Re: SDRAM Timing -
» [SI-LIST] SDRAM Timing -
» [SI-LIST] [SI-LIST]the palcement of bypass/decoupling capacitors -
» [SI-LIST] Re: Ethernet Magnetic Jacks -
» [SI-LIST] Ethernet Magnetic Jacks -
» [SI-LIST] Re: spice modeling for organic build-up substrates -
» [SI-LIST] Re: spice modeling for organic build-up substrates -
» [SI-LIST] Re: chip cap topology - retry -
» [SI-LIST] chip cap topology - retry -
» [SI-LIST] chip cap topology -
» [SI-LIST] Re: Flight time skew due to Dk varation -
» [SI-LIST] Re: spice modeling for organic build-up substrates -
» [SI-LIST] Re: Flight time skew due to Dk varation -
» [SI-LIST] Flight time skew due to Dk varation -
» [SI-LIST] Re: S-parameter use summary -
» [SI-LIST] Re: New Article and Class -
» [SI-LIST] Re: bidirectional line driver needed -
» [SI-LIST] si-list administrivia....... -
» [SI-LIST] SI Engineer Job Opening at Stratus in Maynard, MA -
» [SI-LIST] Re: New Article and Class -
» [SI-LIST] Re: bidirectional line driver needed -
» [SI-LIST] Re: bidirectional line driver needed -
» [SI-LIST] bidirectional line driver needed -
» [SI-LIST] DDR skew -
» [SI-LIST] Hard drive paper posted -
» [SI-LIST] Ethernet Magnetic Jacks -
» [SI-LIST] Re: spice modeling for organic build-up substrates -
» [SI-LIST] spice modeling for organic build-up substrates -
» [SI-LIST] Re: ground plane cut-out pattern for SMA connectors -
» [SI-LIST] Re: Resistor Calculator (off topic) -
» [SI-LIST] Re: HSTL class-III -
» [SI-LIST] Re: SI with IBIS models for ECL devices. -
» [SI-LIST] Re: Resistor Calculator -
» [SI-LIST] ground plane cut-out pattern for SMA connectors -
» [SI-LIST] looking for IBIS models -
» [SI-LIST] Re: S-parameter use summary -
» [SI-LIST] Re: Validate your IBIS models - quickly and completely! -
» [SI-LIST] Validate your IBIS models - quickly and completely! -
» [SI-LIST] European IBIS Summit Announcement -
» [SI-LIST] Re: Lumped vs. Distrbuted systems. -
» [SI-LIST] Re: Lumped vs. Distrbuted systems. -
» [SI-LIST] Re: Lumped vs. Distrbuted systems. -
» [SI-LIST] HSTL class-III -
» [SI-LIST] Re: Resistor Calculator -
» [SI-LIST] Lumped vs. Distrbuted systems. -
» [SI-LIST] [Fwd: Re: Differential Timing in IBIS] -
» [SI-LIST] Re: SI with IBIS models for ECL devices. -
» [SI-LIST] Re: SI with IBIS models for ECL devices. -
» [SI-LIST] Re: SI with IBIS models for ECL devices. -
» [SI-LIST] Re: SI with IBIS models for ECL devices. -
» [SI-LIST] Re: SI with IBIS models for ECL devices. -
» [SI-LIST] Job openings at Sigrity -
» [SI-LIST] Re: SI with IBIS models for ECL devices. -
» [SI-LIST] Re: Parallel Resonance of crystall oscillator -
» [SI-LIST] Re: SI with IBIS models for ECL devices. -
» [SI-LIST] Re: clocking using CPLD -
» [SI-LIST] Re: Parallel Resonance of crystall oscillator -
» [SI-LIST] SI with IBIS models for ECL devices. -
» [SI-LIST] HCSL Ibis Model -
» [SI-LIST] clocking using CPLD -
» [SI-LIST] Re: Parallel Resonance of crystall oscillator -
» [SI-LIST] Re: (no subject) - summary -
» [SI-LIST] Differential Timing in IBIS -
» [SI-LIST] Re: hspice issue -
» [SI-LIST] Re: Ceramic caps -
» [SI-LIST] Re: FR4 non-linear -
» [SI-LIST] Ceramic caps -
» [SI-LIST] vias in flex circuits -
» [SI-LIST] Re: hspice issue -
» [SI-LIST] new paper posted -
» [SI-LIST] Re: Voltage drop across the Inductance -
» [SI-LIST] RMCEMC January Meeting Announcement -
» [SI-LIST] Re: Voltage drop across the Inductance -
» [SI-LIST] Voltage drop across the Inductance -
» [SI-LIST] hspice issue -
» [SI-LIST] Re: Resistor Calculator -
» [SI-LIST] Resistor Calculator -
» [SI-LIST] Re: FR4 non-linear -
» [SI-LIST] FR4 non-linear -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Platform Conference -
» [SI-LIST] Re: 10 Gbps Driver/Receiver IBIS model -
» [SI-LIST] Re: Parallel Resonance of crystall oscillator -
» [SI-LIST] Re: Parallel Resonance of crystall oscillator -
» [SI-LIST] Re: Parallel Resonance of crystall oscillator -
» [SI-LIST] Re: 10 Gbps Driver/Receiver IBIS model -
» [SI-LIST] Re: Parallel Resonance of crystall oscillator -
» [SI-LIST] Planar EM solvers? -
» [SI-LIST] Re: 10 Gbps Driver/Receiver IBIS model -
» [SI-LIST] Re: How to calculate the resistance and inductance of vias -
» [SI-LIST] Re: chip inductors -
» [SI-LIST] Re: How to connect vias to power ground plane? -
» [SI-LIST] Re: Mentor to XTK translation problem -
» [SI-LIST] 10 Gbps Driver/Receiver IBIS model -
» [SI-LIST] Re: SI/Timing tool survey -
» [SI-LIST] SV: Re: Mentor to XTK translation problem -
» [SI-LIST] Re: chip inductors -
» [SI-LIST] Parallel Resonance of crystall oscillator -
» [SI-LIST] Skew boards -
» [SI-LIST] Skew boards -
» [SI-LIST] Re: Wireless board interconnect -
» [SI-LIST] Re: Mentor to XTK translation problem -
» [SI-LIST] Re: Mentor to XTK translation problem -
» [SI-LIST] chip inductors -
» [SI-LIST] Mentor to XTK translation problem -
» [SI-LIST] Re: Wireless board interconnect -
» [SI-LIST] Re: Package model in spectraquest -
» [SI-LIST] Re: SI/Timing tool survey -
» [SI-LIST] Package model in spectraquest -
» [SI-LIST] SI/Timing tool survey -
» [SI-LIST] Senior Signal Integrity Engineer Position Available -
» [SI-LIST] Re: transmission line equations -
» [SI-LIST] transmission line equations -
» [SI-LIST] Wireless board interconnect -
» [SI-LIST] Re: calculating difference impedance for broadside coupled signals -
» [SI-LIST] New Article and Class -
» [SI-LIST] Re: calculating difference impedance for broadside coupled signals -
» [SI-LIST] calculating difference impedance for broadside coupled signals -
» [SI-LIST] How to calculate the resistance and inductance of vias -
» [SI-LIST] pcmcia - typical ibis model -
» [SI-LIST] Re: Regarding Pull down -
» [SI-LIST] Re: Regarding Pull down -
» [SI-LIST] Re: Regarding Pull down -
» [SI-LIST] Re: Regarding Pull down -
» [SI-LIST] Re: Using translated EBD models in Eplanner-scratchpad - Resend -
» [SI-LIST] Re: How to calculate the resistance and inductance of vias -
» [SI-LIST] Using translated EBD models in Eplanner-scratchpad - Resend -
» [SI-LIST] Re: How to calculate the resistance and inductance of vias -
» [SI-LIST] Re: How to calculate the resistance and inductance of vias -
» [SI-LIST] Re: How to calculate the resistance and inductance of vias -
» [SI-LIST] Re: How to calculate the resistance and inductance of vias -
» [SI-LIST] How to calculate the resistance and inductance of vias -
» [SI-LIST] Re: How to calculate the resistance and inductance of vias -
» [SI-LIST] How to calculate the resistance and inductance of vias -
» [SI-LIST] about dc-offset compensation in amplifier -
» [SI-LIST] Re: Regarding Pull down -
» [SI-LIST] USB interconnect question -
» [SI-LIST] More efffects of paths crossing ground plane breaks -
» [SI-LIST] Re: LVDS & TMDS -
» [SI-LIST] LVDS & TMDS -
» [SI-LIST] FW: Using translated EBD models in Eplanner-scratchpad - Resend -
» [SI-LIST] Looking for soft copy of old wl gore paper on eye diagrams..... -
» [SI-LIST] problem about resistor on chip -
» [SI-LIST] Happy New year. -
» [SI-LIST] Happy new year!!!!!!!!!!!!!!!! -