[SI-LIST] Stitching Capacitors, Split-planes & Return Currents ?
- From: "Simba Julian" <sjulian@xxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 27 Mar 2002 14:42:47 -0500
Greetings to all,
I've read numerous publications that have said not to route over split
planes or to avoid splits at all costs. Well, we have dense boards that
require a horde of reference voltages that would force me to have stack-ups
greater than 20 layers. I must split these planes and in my case I have to
send signals directly over these splits.
My Question is.... If I have a 2.0V plane split with a 1.5V rail should I
place two capacitors, one on each side of the split to the nearest ground
plane. Or should I place one capacitor across the split connecting both
Voltage rails (on the same layer). In both cases, we are assuming that the
signals of concern are on the layer adjacent to the split.
In my eyes the second case seems more attractive.... Lower capacitor count,
half the inductance (ESL of one cap as opposed to two) for the return path,
real estate. Nonetheless, are there any issues that I may be overlooking in
regard to capacitivly (is that how you spell it?) tying two power planes?
Would it matter if the difference between the planes were larger.... Such as
5V and 2V? Are there any drawbacks to this configuration whereby the first
scenario provides a better return/design?
Secondly,
My assumptions is that the largest capacitor with the smallest ESL would be
optimal. Say ...... I'll use 0.1u for stitching, Is there any guide two
determining the circle of influence for a capacitor based on capacitance
(This should guide the number of capacitors needed for this application....
And is probably useful for determining bulk capacitor count in the
decoupling realm). I'll probably need a few since I have quite a few nets
and different busses crossing this split, but I just wouldn't want to over
do it!!!
Thanks... I Really appreciate all responses,
Simba
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