[SI-LIST] Re: Stitching Capacitors, Split-planes & Return Currents ?
- From: Wang Xiao-yun <wangxiaoyun@xxxxxxxxx>
- To: sjulian@xxxxxxx
- Date: Thu, 28 Mar 2002 17:39:26 +0800
Hello, Simba:
Are you sure the signals whose return current concerns are using the
power plane as reference rather than the continuous ground plane?
I'm doing design with voltage supplies ranging from 1.5V to 2.5V,
besides the main 3.3V, but those voltages are used as core power supply
for many large chips. It seems to me not a good idea to have core
voltage supply as a path for return currents. My understanding is when
you decide to jump the current from one reference plane to the other via
a cap as in your case, you have to provide another cap somewhere to lead
the current back to the original plane before it finally goes back to
the its source.
Moreover, quite a few chips I'm dealing with consume most of their
currents in cores. Connecting capacitors between different planes
provides paths to let the large current going anywhere it can. It does
not seem safe to me.
I'm also suffering from the fact that different power supplies exist
almost everywhere on my board, but my limited ken stops me from doing
what you are considering. I would also like to hear any gurus to provide
some better ways in dealing with the problem.
Regards.
Simba Julian wrote:
>Greetings to all,
>
>I've read numerous publications that have said not to route over split
>planes or to avoid splits at all costs. Well, we have dense boards that
>require a horde of reference voltages that would force me to have stack-ups
>greater than 20 layers. I must split these planes and in my case I have to
>send signals directly over these splits.
>
>My Question is.... If I have a 2.0V plane split with a 1.5V rail should I
>place two capacitors, one on each side of the split to the nearest ground
>plane. Or should I place one capacitor across the split connecting both
>Voltage rails (on the same layer). In both cases, we are assuming that the
>signals of concern are on the layer adjacent to the split.
>
>In my eyes the second case seems more attractive.... Lower capacitor count,
>half the inductance (ESL of one cap as opposed to two) for the return path,
>real estate. Nonetheless, are there any issues that I may be overlooking in
>regard to capacitivly (is that how you spell it?) tying two power planes?
>Would it matter if the difference between the planes were larger.... Such as
>5V and 2V? Are there any drawbacks to this configuration whereby the first
>scenario provides a better return/design?
>
>
>Secondly,
>My assumptions is that the largest capacitor with the smallest ESL would be
>optimal. Say ...... I'll use 0.1u for stitching, Is there any guide two
>determining the circle of influence for a capacitor based on capacitance
>(This should guide the number of capacitors needed for this application....
>And is probably useful for determining bulk capacitor count in the
>decoupling realm). I'll probably need a few since I have quite a few nets
>and different busses crossing this split, but I just wouldn't want to over
>do it!!!
>
>
>Thanks... I Really appreciate all responses,
>Simba
>
>
>
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