[SI-LIST] Re: Stack up for EMI reduction
- From: Ahmad Fallah <emcesd2000@xxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 2 Feb 2004 09:18:38 -0800 (PST)
Hello Nima,
The layer 8 of the current stack up may be the main cause of the EMI issues you
are dealing with, if signal traces on layers 7 and 9 are crossing the splits in
the power plane. Making this layer a solid power plane should help with the
current stack up's performance.
Layer 8 of the "new proposed stack up " may result in the some EMI issues
(though less pronounced than the old design), again if signals cross the
splits. I am assuming that the signals on layer 7 are tightly coupled to GND
on layer 6, however, layer 8 is playing a role in determining the line
impedance of those traces in layer 7. Any discontinuities in the return path
should be accounted for. Simulation tools will aid you in determining the
dimensional parameters for desired signal line characteristics impedance.
Another issue I see with the proposed stack up is using the layers 2 and 9 for
breakout (escapes). When these layers are used as breakout in the BGA areas
(assuming 1-mm pitch), most or all of the copper in these areas is removed--
hence reducing or eliminating the power plane capacitance.
It is believed by some that the thin slivers of copper left in the BGA areas is
providing enough power/GND plane pair decoupling, which I do not agree with.
The reduction of copper in the BGA areas is only one part of the problem (i.e.,
directly proportional to reduction in the plane capacitance), however, the
inductive patterns formed by the remaining copper slivers is the main issue.
We have a paper on this topic that was published in the 2003 EMC symposium
proceedings, and we have submitted a follow-up paper for this year.
Please consider the following stack up:
1 TOP (Escapes/power)
2 GND (solid)
3 SIG
4 Power (solid) [core supply]
5 GND (solid)
6 SIG (GND flood)
7 Power (solid) [I/O supply]
8 SIG (GND flood)
9 GND
10 BOTTOM (Escapes/power)
This stack up will provide three routing/signal layers, while maintaining the
return path integrity. In conjunction with this, one can also flood the unused
areas of the signal layers with power signals of alternating polarity in order
to increase the plane-pair decoupling. Please note that this stack up does not
yield itself well to the use of ZBC 2000 (Sanmina-SCI's buried capacitance), as
this process requires that a core exist between the PWR and GND planes. The
proposed stack up uses prepreg for the PWR/GND plane pair
Kind Regards,
Ahmad
408-309-7468
Nima Lotfi <lnima@xxxxxxxxxxxxxxxxxx> wrote:
Hi,
I'm looking at re-layout of a 10 layer board because of EMI problems. The
board contains 4 differential serial signals a ~700Mhz, and about 20 single
ended signals at 70 MHz. The main problem frequencies are around 350 Mhz.
There are 4 large BGA components on the board.
I would ideally like to move into a 12 layer board, however there is quite a
bit of (non technical) resistance to doing that.
I like to eliminate 2 signal layers, by making my other 2 signal layer
denser. Then I'll use the eliminated signal layers as ground/power layers,
but I will need to use these new gnd/power layers to assist with breakout of
4 high density (500pins) BGA.
My question is can any one comment on whether I should in theory get an EMI
improvement? What should I look out for?
My current stack up is:
1 Mainly GND with some breakout
2 Signal
3 Gnd
4 Signal
5 Power
6 Gnd
7 Signal
8 GND/Power (mixed)
9 Signal
10 mainly GND with some breakout
New proposed stack up
1 GND with some breakout
2 power with some breakout
3 Gnd
4 Signal
5 Power
6 Gnd
7 Signal
8 GND/Power (mixed)
9 Power with some breakout
10 mainly GND with some breakout
Thanks,
Nima
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