[SI-LIST] Re: Stack up for EMI reduction

Ahmad, I shudder whenever people refer to plane capacitance.  At short=20
distances, where a section of the plane could be considered lumped, the=20
capacitance is so small as almost always be insignificant.  At greater=20
distances, the planes behave as transmission lines and there is no lumped=20
capacitor to draw on.  I strongly advocate looking at the planes as only an=
=20
impedance between the decoupling capacitors and the load IC.  It there is=20
lots of "capacitance" it is part of a low impedance transmission line.

As far as placing capacitors on the package, yes to cover frequencies where=
=20
the interconnect to the PWB impedance is too high, the IC must provide=20
charge storage.  But the practical limits of that storage are pretty low,=20
limiting the low frequency cut-off.

Capacitors don't "have to" have multiple vias, but it does save otherwise=20
unnecessary parts, as the mounted inductance sets the high frequency=20
impedance that has to reach up to the low frequency cut-off of the IC.

Thanks for the paper reference.

Steve.

At 08:25 AM 2/4/2004 -0800, Ahmad Fallah wrote:
>Hello Steve,
>
>I would like to make a clarification of a point you have brought=20
>up.  Having the web/grid of copper is by far better than not having any=20
>form of plane (in the BGA areas), but reliance on this perforated plane as=
=20
>the only means of decoupling and not needing/using any discrete capacitors=
=20
>(a point that I have heard from some in this forum) is the point of=
 contention.
>
>
>
>If one uses the PWR and GND planes as escapes/breakouts then one may=20
>totally give up the benefits that even those perforated planes=20
>provide.  Going back to the decoupling topic that has been discussed at=20
>length, for the high-speed chips, the decoupling (capacitor) must be=20
>placed on the package itself to be effective.  And/or the pinout must be=20
>designed so to support the access of PWR and GND pins to the =93solid=94=20
>planes on the periphery of the BGA arrays, and to accommodate the use of=20
>discrete capacitors mounted by multiple vias.
>
>
>Aside from these points, one needs to examine the placement and routing=20
>design of the board under discussion.  For example, in one OC-192 line=20
>card, the SERDES were placed too close to the =AD48 V traces and=
 components,=20
>and the noise was coupling onto the power lines.  Also, the =AD48 V traces=
=20
>were buried among 22 layers the length of connection between the input to=
=20
>the board and the DC/DC converters.  I measured more than 18 dB of=20
>difference in the SSN levels between the input to DC/DC bricks and the=20
>input to the board connector.
>
>Following is the information for our paper.
>
>
>On Characterizing the Impedance of Power/Ground
>
>Planes- Including the Effect of Anti-Pads
>
>
>Alireza Mahanfar
>IRCOM
>
>Limoges, France
>
>nima.mahanfar@xxxxxxxx
>
>
>
>Ahmad Mahin Fallah
>
>Independent Consultant
>
>Cupertino, CA, USA
>
>AhmadFallah@xxxxxxxx
>
>
>
>Robert M. Nelson
>
>North Dakota State University
>
>Fargo, ND, USA
>
>R.M.Nelson@xxxxxxxx
>
>
>
>Kind regards,
>Ahmad
>
>steve weir <weirsp@xxxxxxxxxx> wrote:
>Ahmad, I didn't see your paper. I think the key to keeping a web under the
>BGA's is to prevent creation of a giant inductor.
>
>Regards,
>
>Steve.
>At 09:18 AM 2/2/2004 -0800, Ahmad Fallah wrote:
> >Hello Nima,
> >
> >
> >
> >The layer 8 of the current stack up may be the main cause of the EMI
> >issues you are dealing with, if signal traces on layers 7 and 9 are
> >crossing the splits in the power plane. Making this layer a solid power
> >plane should help with the current stack up's performance.
> >
> >
> >
> >Layer 8 of the "new proposed stack up " may result in the some EMI issues
> >(though less pronounced than the old design), again if signals cross the
> >splits. I am assuming that the signals on layer 7 are tightly coupled to
> >GND on layer 6, however, layer 8 is playing a role in determining the=
 line
> >impedance of those traces in layer 7. Any discontinuities in the return
> >path should be accounted for. Simulation tools will aid you in=
 determining
> >the dimensional parameters for desired signal line characteristics=20
> impedance.
> >
> >
> >
> >Another issue I see with the proposed stack up is using the layers 2 and=
 9
> >for breakout (escapes). When these layers are used as breakout in the BGA
> >areas (assuming 1-mm pitch), most or all of the copper in these areas is
> >removed-- hence reducing or eliminating the power plane capacitance.
> >
> >
> >
> >It is believed by some that the thin slivers of copper left in the BGA
> >areas is providing enough power/GND plane pair decoupling, which I do not
> >agree with. The reduction of copper in the BGA areas is only one part of
> >the problem (i.e., directly proportional to reduction in the plane
> >capacitance), however, the inductive patterns formed by the remaining
> >copper slivers is the main issue. We have a paper on this topic that was
> >published in the 2003 EMC symposium proceedings, and we have submitted a
> >follow-up paper for this year.
> >
> >
> >
> >Please consider the following stack up:
> >
> >
> >
> >1 TOP (Escapes/power)
> >
> >2 GND (solid)
> >
> >3 SIG
> >
> >4 Power (solid) [core supply]
> >
> >5 GND (solid)
> >6 SIG (GND flood)
> >
> >7 Power (solid) [I/O supply]
> >
> >8 SIG (GND flood)
> >
> >9 GND
> >
> >10 BOTTOM (Escapes/power)
> >
> >
> >
> >This stack up will provide three routing/signal layers, while maintaining
> >the return path integrity. In conjunction with this, one can also flood
> >the unused areas of the signal layers with power signals of alternating
> >polarity in order to increase the plane-pair decoupling. Please note that
> >this stack up does not yield itself well to the use of ZBC 2000
> >(Sanmina-SCI's buried capacitance), as this process requires that a core
> >exist between the PWR and GND planes. The proposed stack up uses prepreg
> >for the PWR/GND plane pair
> >
> >
> >
> >Kind Regards,
> >
> >
> >
> >Ahmad
> >
> >408-309-7468
> >
> >
> >
> >
> >
> >Nima Lotfi wrote:
> >Hi,
> >I'm looking at re-layout of a 10 layer board because of EMI problems. The
> >board contains 4 differential serial signals a ~700Mhz, and about 20=
 single
> >ended signals at 70 MHz. The main problem frequencies are around 350 Mhz.
> >There are 4 large BGA components on the board.
> >
> >I would ideally like to move into a 12 layer board, however there is=
 quite a
> >bit of (non technical) resistance to doing that.
> >
> >I like to eliminate 2 signal layers, by making my other 2 signal layer
> >denser. Then I'll use the eliminated signal layers as ground/power=
 layers,
> >but I will need to use these new gnd/power layers to assist with breakout=
 of
> >4 high density (500pins) BGA.
> >
> >My question is can any one comment on whether I should in theory get an=
 EMI
> >improvement? What should I look out for?
> >
> >
> >My current stack up is:
> >
> >1 Mainly GND with some breakout
> >2 Signal
> >3 Gnd
> >4 Signal
> >5 Power
> >6 Gnd
> >7 Signal
> >8 GND/Power (mixed)
> >9 Signal
> >10 mainly GND with some breakout
> >
> >
> >
> >New proposed stack up
> >
> >1 GND with some breakout
> >2 power with some breakout
> >3 Gnd
> >4 Signal
> >5 Power
> >6 Gnd
> >7 Signal
> >8 GND/Power (mixed)
> >9 Power with some breakout
> >10 mainly GND with some breakout
> >
> >
> >Thanks,
> >Nima
> >
> >
> >
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