[SI-LIST] Re: Stack up for EMI reduction

You can calculate the plane resonance that results from the transmission 
line dimensions with a hand calculator.  A think to avoid is a board 
geometry that naturally aligns with a primary clock or signal frequency.

However, determining parallel resonant frequencies and amplitudes of the 
plane reactance with discrete components with any accuracy requires a model 
that includes placement of the components.  This is especially true with 
high K dielectrics.  High K dielectrics have their place, but they are no 
panacea, and used carelessly can cause resonances at pretty low, < 100MHz 
frequencies.  The best thing about the high K dielectrics is that at least 
they are lossy.

Regards,


Steve.
At 08:52 PM 1/31/2004 +0800, zhangkun 29902 wrote:
>Dear Nima
>
>According to my experience, in the power integrity of PCB, there are 
>always some anti-resinance pole at about 200MHz-400MHz. Could you tell me 
>the dimesion of your PCB?
>
>These kind of poless are because of resonance between discrete caps and 
>plane caps. In this situation, some thin dielectric(<3mil) should be used 
>in the stack-up. If the embedded cap is not useful, I suggust you to use 
>some termination in the power supply net. This will eliminate the  poles.
>
>Besides the measurement about EMI, some power integrity analysis at PCB 
>level is suggested.
>
>I hope this will help.
>
>Best Regards
>
>Zhangkun
>2004.1.31
>
>----- Original Message -----
>From: Nima Lotfi <lnima@xxxxxxxxxxxxxxxxxx>
>Date: Saturday, January 31, 2004 7:11 am
>Subject: [SI-LIST] Stack up for EMI reduction
>
> > Hi,
> > I'm looking at re-layout of a 10 layer board because of EMI
> > problems.  The
> > board contains 4 differential serial signals a ~700Mhz, and about
> > 20 single
> > ended signals at 70 MHz.  The main problem frequencies are around
> > 350 Mhz.
> > There are 4 large BGA components on the board.
> >
> > I would ideally like to move into a 12 layer board, however there
> > is quite a
> > bit of (non technical) resistance to doing that.
> >
> > I like to eliminate 2 signal layers, by making my other 2 signal layer
> > denser.  Then I'll use the eliminated signal layers as
> > ground/power layers,
> > but I will need to use these new gnd/power layers to assist with
> > breakout of
> > 4 high density (500pins) BGA.
> >
> > My question is can any one comment on whether I should in theory
> > get an EMI
> > improvement?  What should I look out for?
> >
> >
> > My current stack up is:
> >
> > 1 Mainly GND with some breakout
> > 2 Signal
> > 3 Gnd
> > 4 Signal
> > 5 Power
> > 6 Gnd
> > 7 Signal
> > 8 GND/Power (mixed)
> > 9 Signal
> > 10 mainly GND with some breakout
> >
> >
> >
> > New proposed stack up
> >
> > 1 GND with some breakout
> > 2 power with some breakout
> > 3 Gnd
> > 4 Signal
> > 5 Power
> > 6 Gnd
> > 7 Signal
> > 8 GND/Power (mixed)
> > 9 Power with some breakout
> > 10 mainly GND with some breakout
> >
> >
> > Thanks,
> > Nima
> >
> >
> >
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