[SI-LIST] Re: Single ended Noise OR Differential Noise
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 07 Oct 2014 12:14:38 -0700
All voltage noise between a single-ended transmitter and receiver causes
jitter. Single ended jitter is minimized by: Launching against a
single reference, propagating the transmit energy against that same
reference, and tightly coupling the receiver threshold voltage to that
same reference.
Steve.
On 10/7/2014 6:10 AM, Naresh Dhamija wrote:
> Hi folks,
>
> I am doing power noise analysis on a system that uses SSTL IO buffers. I
> am seeing the ripple on the IO output signal - such that during hi state
> IO output signal follows the noise whatever is on the vddio and during low
> state, IO output signal follows the noise on the vss. Observing this
> phenomenon, I purposely forced IN PHASE single ended noise to both vdddio
> and vss of almost the same frequency as of data rate but uncorrelated with
> data rate. Since noise forced to vddio and vss are IN PHASE so
> Differential Noise measured between vddio and vss at each instant shows
> zero noise. But still I see jitter on the edges because of finite rise and
> fall times, the initial low level and final high level for a transition
> from low to hi are not always same. Does this mean that along with
> differential noise, single ended noise on power and ground also cause
> jitter to IO driver.
>
> Regards
> Naresh
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