Hi folks, I am doing power noise analysis on a system that uses SSTL IO buffers. I am seeing the ripple on the IO output signal - such that during hi state IO output signal follows the noise whatever is on the vddio and during low state, IO output signal follows the noise on the vss. Observing this phenomenon, I purposely forced IN PHASE single ended noise to both vdddio and vss of almost the same frequency as of data rate but uncorrelated with data rate. Since noise forced to vddio and vss are IN PHASE so Differential Noise measured between vddio and vss at each instant shows zero noise. But still I see jitter on the edges because of finite rise and fall times, the initial low level and final high level for a transition from low to hi are not always same. Does this mean that along with differential noise, single ended noise on power and ground also cause jitter to IO driver. Regards Naresh ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List forum is accessible at: http://tech.groups.yahoo.com/group/si-list List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu