[SI-LIST] Re: Placement of decoupling capacitors
- From: Khalid Ansari <khalida@xxxxxxxxxxx>
- To: Raymond.Anderson@xxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Tue, 31 Jul 2001 16:03:56 -0700
At 02:53 PM 7/31/01 -0700, Ray Anderson wrote:
>Khalid Ansari wrote:
> >
> >I just have enough space to place this one close to the pin, the rest have
> >to go quite further away due to space constraint. Placing them too far
> >away I have to worry about the loop inductance.
> >
>
> The loop inductance you need to be concerned with is
> that of the loop formed by the decap, the mounting pads,
> vias and power planes. The distance between the decap
> and the IC doesn't determine the loop inductance.
>
> That being said, the distance IS an issue when you consider
> the time of flight between the decap and the IC consuming
> the current. A commonly used rule-of-thumb is that
> the decap should be within 1/10 wavelength (at the frequency
> of interest) of the chip it is supplying in order to be effective.
Thanks for your input. I am not very clear on what you mean by
the frequency of interest. Is it the frequency range where the cap.
is most effective (frequency of resonance, ex. 232 MHz for a 470 pf
cap.) or the freq. that the device is running at. If it is the freq. the
device is running at then what I understand from your email, all the
capacitors should be at the same distance from the IC because they
are all supplying the same IC.
According to you the distance between the cap. and IC does not
effect the loop inductance. If this is the case then why can we get
away by placing the smallest capacitor closest to the pin and the
once with the bigger values away?
> If you are too far away, the chip requiring the current may not
> get it in time from the decap sourcing the current.
>
>-Ray Anderson
>Sun Microsystems Inc.
Khalid
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