[SI-LIST] Re: PDN Question
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Joel Brown <joel@xxxxxxxxxx>
- Date: Thu, 08 Apr 2010 19:28:55 -0700
Joel, the idea of a limited useful frequency range of a bypass capacitor
is a misnomer. The mounted SRF sets a frequency range where the
capacitor is most effective due to beneficial phase cancellation. It is
an optimum operating frequency range, not the only effective range. The
basic and fundamental issue is and always will be impedance, which at
any frequency above audio is dominated by inductance, and resonances
that are controlled by inductance. If you had a mythical 1F, 1mOhm, 1pH
capacitor, it would have an SRF of only 160kHz. Yet, if we didn't have
limitations in the interconnects, that one cap would yield a flat
(+/-3dB) resistive frequency response from 160Hz out to 160MHz.
Putting power planes in the middle of a PCB may seem like a good idea,
but it is very costly in terms of bypass caps, as well as the attachment
inductance of the ICs. It works OK where the IC has been designed for it
through a combination of the in-package/on-die energy storage and the
number of power / ground via pairs that come out of the package. If that
combination does not satisfy the requirements of the IC, then exercising
the right combination of data patterns in the part will cause bad things
to happen. This is an ongoing industry issue and it has burned many.
This presentation:
http://www.ipblox.com/pubs/SVCEMC_Feb_2006/stack_up_vias_pdn_public.pdf
discusses the issues of stack-up and power delivery in greater detail.
Best Regards,
Steve.
Joel Brown wrote:
> Currently I am using the Altera PDN tool for Stratix III.
> With the values I entered the target impedance is 0.012 ohms.
>
> There is also Feffective of 59 MHz.
>
> The users manual states that using PCB capacitors for PDN
>
> decoupling beyond their effective frequency range brings little improvement
> to PDN
>
> performance and raises the bill of materials (BOM) cost.
>
>
>
> So my first question would be why is it ok to not provide bypassing beyond
> this Feffective frequency?
>
> I do realize that it may not be possible to do this which what I think is
> what Altera is saying.
>
> But what will prevent the noise voltage from exceeding limits above this
> frequency?
>
> I do know that Altera has internal bypass capacitors on these parts but
> there is no information on their characteristics.
>
>
>
> Most of our board designs use power planes in the center of the board.
>
> Here is an example stackup:
>
>
>
> Layer 1: Component side / Signals
>
> Layer 2: Ground Plane
>
> Layer 3: Signal 1
>
> Layer 4: Signal 2
>
> Layer 5: Ground Plane
>
> Layer 6: Power Plane
>
> Layer 7: Power Plane
>
> Layer 8: Ground Plane
>
> Layer 9: Signal 3
>
> Layer 10: Signal 4
>
> Layer 11: Ground Plane
>
> Layer 12: Solder side / Signals
>
>
>
> We do this to reduce layer count and so the split power planes are
> surrounded by solid ground planes.
>
> In trying to achieve 0.012 ohm target impedance out to 59 MHz I found that I
> reached a point of diminishing returns and no matter how many bypass caps I
> used I could not really get there even with X2Y caps. By playing around I
> found that reducing the inductance by moving the power planes closer to the
> top layer I could achieve the target impedance. But this would mean a
> different stackup:
>
>
>
> Layer 1: Component side / Signals
>
> Layer 2: Ground Plane
>
> Layer 3: Power Plane
>
> Layer 4: Power Plane
>
> Layer 5: Ground Plane
>
> Layer 6: Signal 1
>
> Layer 7: Ground Plane
>
> Layer 8: Signal 2
>
> Layer 9: Signal 3
>
> Layer 10: Ground Plane
>
> Layer 11: Signal 4
>
> Layer 12: Ground Plane
>
> Layer 13: Power Plane
>
> Layer 14: Power Plane
>
> Layer 15: Ground Plane
>
> Layer 16: Solder side / Signals
>
>
>
> Now the board has gone from 12 layers to 16 layers and the power planes on
> layers 13 and 14 are of no use for high frequency bypassing.
>
>
>
> My next question would be is it possible to use a slightly asymmetrical
> stack up like this:
>
>
>
> Layer 1: Component side / Signals
>
> Layer 2: Ground Plane
>
> Layer 3: Power Plane
>
> Layer 4: Power Plane
>
> Layer 5: Ground Plane
>
> Layer 6: Signal 1
>
> Layer 7: Signal 2
>
> Layer 8: Ground Plane
>
> Layer 9: Signal 3
>
> Layer 10: Signal 4
>
> Layer 11: Ground Plane
>
> Layer 12: Solder side / Signals
>
>
>
> The copper weight of the power planes would be ½ oz to match Signal layers 9
> and 10.
>
> Would this be manufacturable? Would any special technology be required?
>
> I keep hearing that boards with asymmetrical stack ups will warp too much.
>
>
>
> Thanks – Joel
>
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--
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV 89501
www.ipblox.com
(775) 299-4236 Business
(866) 675-4630 Toll-free
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