[SI-LIST] Re: PDN Question
- From: "Han, Guobing" <han.guobing@xxxxxxxxx>
- To: "Traa, Boris" <boris.traa@xxxxxxxxxxx>
- Date: Fri, 20 Aug 2010 09:34:38 +0800
Fserial~= 1/2/pi/sqrt(C*(ESL+Lloop_dieside)),
Fparellel~= 1/2/pi/sqrt(C*(ESL+Lloop_ballside)),
with the assumption: Lloop_ballside>>Lloop_dieside>>ESL
-Guobing
2010/8/20, Han, Guobing <han.guobing@xxxxxxxxx>:
> Hi Boris,
>
> Yes, you're right. However I just wanted to emphasize the
> importance of Lloop compared with ESL.
> There are many resonant modes due to the complicated distributed
> network. This formula is just a simple one to estimate one resonant
> frequency due to specific DECAP.
> For example, the DECAP is located near the die side of one power
> net, and the ball side is shorted at AC mode (VRM), this formula often
> estimate the close resonant frequency point.
>
> Thanks,
> Guobing
>
> 2010/8/19, Traa, Boris <boris.traa@xxxxxxxxxxx>:
>> Dear Guobing,
>>
>> If you want to use the formule f=1/2/pi/sqrt((Lloop+ESL)*C) you should
>> know
>> how the ESL is defined, determined and measured. If the circumstances in
>> your application (e.q. the distance between the capacitor and the ground
>> plane) differ from the ESL measurement set up than the use of your
>> formula
>> is doubtful.
>> In addition I think that in case the thickness of the capacitor is not
>> negligible to its ground plane distance the capacitor cannot be
>> substituted
>> by only one capacitance with one series inductance. In my opinion the
>> capacitor will contain many LC circuits in parallel with different values
>> for these L's and C's while these L's and C's might be frequency
>> dependent
>> too.
>>
>> Kind regards
>> Boris Traa
>> System design engineer EMC
>>
>> It's the currents that make circuits work or fail.
>>
>> Philips Applied Technologies/EMC center
>> Room 2.020
>> High Tech Campus 26
>> 5656AE Eindhoven, The Netherlands
>> Tel: ++ 31 40 27 43766
>> Fax: ++ 31 40 27 42224
>> E-mail: boris.traa@xxxxxxxxxxx
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> On
>> Behalf Of Han, Guobing
>> Sent: 2010 Aug 19 10:36 AM
>> To: Istvan Novak
>> Cc: Joel Brown; si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: PDN Question
>>
>> Hi Joel,
>> The effective frequency provided is from the formula
>> f=1/2/pi/sqrt(ESL*C) . However,in practical, the loop inductance is
>> greater than ESL and so dominate the real resonant frequency.
>> Thus, the formula should be modified by
>> f=1/2/pi/sqrt((Lloop+ESL)*C) . Please change the 100nF to 10nF, 1nF,
>> even 0.1nF may help to your designs.
>>
>>
>> Thanks,
>> Guobing
>>
>>
>> 2010/4/8, Istvan Novak <istvan.novak@xxxxxxx>:
>>> Hi Joel,
>>>
>>> These are the usual dilemmas in many designs.
>>>
>>> Just a few quick comments:
>>> - if you need to lower the cumulative inductance from your capacitors,
>>> you can consider
>>> using multiple vias per pad. Downside: with your planes in the middle of
>>> the stack, more
>>> vias will block more routing unless you do backdrilling or sequential
>>> lamination.
>>> - the bottom side of the board is not necessarily useless for
>>> low-inductance PDN.
>>> Consider the case when a consumer has multiple power/ground vias
>>> (typical for FPGA core).
>>> The multiple vias can connect to the surface effectively, so if you had
>>> your power plane
>>> closer to the bottom, it could still be connected with relatively low
>>> inductance to the
>>> package on the top side and you could bypass it with fewer caps on the
>>> bottom.
>>> Alternately you could leave the planes in the middle and see if you can
>>> add bypass
>>> capacitors directly across the power/ground pins on the bottom. This
>>> will depend on
>>> many factors, but it is becoming more widely available.
>>> - your asymmetrical stackup may work well if the board is small or if
>>> the assembly
>>> can live with some warpage. I would not do this on large boards, because
>>> the copper
>>> utilization is very different on signal versus power layers.
>>>
>>> Regards,
>>>
>>> Istvan Novak
>>> Oracle-Sun
>>>
>>> Joel Brown wrote:
>>>> Currently I am using the Altera PDN tool for Stratix III.
>>>> With the values I entered the target impedance is 0.012 ohms.
>>>>
>>>> There is also Feffective of 59 MHz.
>>>>
>>>> The users manual states that using PCB capacitors for PDN
>>>>
>>>> decoupling beyond their effective frequency range brings little
>>>> improvement
>>>> to PDN
>>>>
>>>> performance and raises the bill of materials (BOM) cost.
>>>>
>>>>
>>>>
>>>> So my first question would be why is it ok to not provide bypassing
>>>> beyond
>>>> this Feffective frequency?
>>>>
>>>> I do realize that it may not be possible to do this which what I think
>>>> is
>>>> what Altera is saying.
>>>>
>>>> But what will prevent the noise voltage from exceeding limits above
>>>> this
>>>> frequency?
>>>>
>>>> I do know that Altera has internal bypass capacitors on these parts but
>>>> there is no information on their characteristics.
>>>>
>>>>
>>>>
>>>> Most of our board designs use power planes in the center of the board.
>>>>
>>>> Here is an example stackup:
>>>>
>>>>
>>>>
>>>> Layer 1: Component side / Signals
>>>>
>>>> Layer 2: Ground Plane
>>>>
>>>> Layer 3: Signal 1
>>>>
>>>> Layer 4: Signal 2
>>>>
>>>> Layer 5: Ground Plane
>>>>
>>>> Layer 6: Power Plane
>>>>
>>>> Layer 7: Power Plane
>>>>
>>>> Layer 8: Ground Plane
>>>>
>>>> Layer 9: Signal 3
>>>>
>>>> Layer 10: Signal 4
>>>>
>>>> Layer 11: Ground Plane
>>>>
>>>> Layer 12: Solder side / Signals
>>>>
>>>>
>>>>
>>>> We do this to reduce layer count and so the split power planes are
>>>> surrounded by solid ground planes.
>>>>
>>>> In trying to achieve 0.012 ohm target impedance out to 59 MHz I found
>>>> that
>>>> I
>>>> reached a point of diminishing returns and no matter how many bypass
>>>> caps
>>>> I
>>>> used I could not really get there even with X2Y caps. By playing around
>>>> I
>>>> found that reducing the inductance by moving the power planes closer to
>>>> the
>>>> top layer I could achieve the target impedance. But this would mean a
>>>> different stackup:
>>>>
>>>>
>>>>
>>>> Layer 1: Component side / Signals
>>>>
>>>> Layer 2: Ground Plane
>>>>
>>>> Layer 3: Power Plane
>>>>
>>>> Layer 4: Power Plane
>>>>
>>>> Layer 5: Ground Plane
>>>>
>>>> Layer 6: Signal 1
>>>>
>>>> Layer 7: Ground Plane
>>>>
>>>> Layer 8: Signal 2
>>>>
>>>> Layer 9: Signal 3
>>>>
>>>> Layer 10: Ground Plane
>>>>
>>>> Layer 11: Signal 4
>>>>
>>>> Layer 12: Ground Plane
>>>>
>>>> Layer 13: Power Plane
>>>>
>>>> Layer 14: Power Plane
>>>>
>>>> Layer 15: Ground Plane
>>>>
>>>> Layer 16: Solder side / Signals
>>>>
>>>>
>>>>
>>>> Now the board has gone from 12 layers to 16 layers and the power planes
>>>> on
>>>> layers 13 and 14 are of no use for high frequency bypassing.
>>>>
>>>>
>>>>
>>>> My next question would be is it possible to use a slightly asymmetrical
>>>> stack up like this:
>>>>
>>>>
>>>>
>>>> Layer 1: Component side / Signals
>>>>
>>>> Layer 2: Ground Plane
>>>>
>>>> Layer 3: Power Plane
>>>>
>>>> Layer 4: Power Plane
>>>>
>>>> Layer 5: Ground Plane
>>>>
>>>> Layer 6: Signal 1
>>>>
>>>> Layer 7: Signal 2
>>>>
>>>> Layer 8: Ground Plane
>>>>
>>>> Layer 9: Signal 3
>>>>
>>>> Layer 10: Signal 4
>>>>
>>>> Layer 11: Ground Plane
>>>>
>>>> Layer 12: Solder side / Signals
>>>>
>>>>
>>>>
>>>> The copper weight of the power planes would be ½ oz to match Signal
>>>> layers
>>>> 9
>>>> and 10.
>>>>
>>>> Would this be manufacturable? Would any special technology be required?
>>>>
>>>> I keep hearing that boards with asymmetrical stack ups will warp too
>>>> much.
>>>>
>>>>
>>>>
>>>> Thanks - Joel
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>
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>>
>>
>> --
>> Thanks,
>> - Robin (Han, Guobing)
>> TEL: 86-21-61094805
>> MSN: han_guobing@xxxxxxxxxxx
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>
>
> --
> Thanks,
> - Robin (Han, Guobing)
> TEL: 86-21-61094805
> MSN: han_guobing@xxxxxxxxxxx
>
--
Thanks,
- Robin (Han, Guobing)
TEL: 86-21-61094805
MSN: han_guobing@xxxxxxxxxxx
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