[SI-LIST] Re: On-Chip Parasitic C & its effect on R
- From: steve weir <weirsi@xxxxxxxxxx>
- To: xileil@xxxxxxxxxxx
- Date: Sun, 18 Nov 2007 19:56:02 -0800
Xilei, you can improve frequency response flatness with equalization of=20
one form or another. A shunt inductor / resistor combination can drop=20
the low frequency response to compensate for what the shunt capacitance=20
takes from the high frequency. It is important that the parameters are=20
controlled well enough that you can adequately damp the response at the=20
parallel resonance, or you will suffer big amplitude and phase shifts.
Steve.
Xilei Liu wrote:
> Dave,
> =20
> Will a varistor (shunt), inductor (series) help for this case? I don't=
have any simulator to try. Thanks.
> =20
> Regards,
> Celine > Date: Thu, 15 Nov 2007 20:03:42 -0700> From: telegrapher9@gmai=
l.com> To: jeetshah@xxxxxxxxx> Subject: [SI-LIST] Re: On-Chip Parasitic C=
& its effect on R> CC: si-list@xxxxxxxxxxxxx> > Jitesh,> > does your chi=
p have ODT? I ran a frequency domain sim using an> electronic Smith Chart=
and adding an inductor didn't help. I'm able to> rapidly sweep various c=
omponent values and did not obtain good return> loss until adding some se=
ries resistance. Of course to keep the delay> low and not attentuate the =
signal too much this value I limited to 25> ohms. Here is the model:> > 1=
2 ps, 50 ohm t-line. 50 ohm ODT shunt. 25 ohms series resistor. 400> fF s=
hunt, 5 ohm series, 400 fF shunt.> > This was modeled single-ended. Your =
application is differential, is> it? Also, the 25 ohm series resistor iso=
lates the ESD circuitry. Not> good but this might lead to some more insig=
ht into this matching> problem. The ESD circuitry and driver/receiver are=
modeled as the 400> fF, 5 ohm, 400 fF.> >=20
> Dave Cuthbert> Consultant> > > On Nov 15, 2007 5:48 PM, Jitesh Shah <j=
eetshah@xxxxxxxxx> wrote:> > Hi Everybody,> >> > I am designing a flip ch=
ip package for multi-Gbps> > SerDes (6.25Gbps & above) where as a stand a=
lone> > package, I am able to optimize the flip-chip> > interconnect stru=
cture to meet the return loss> > specification of 10dB for up to 2x the f=
undamental> > switching frequency i.e., 10GHz.> >> > But due to the on-ch=
ip parasitic capacitance (~800fF)> > associated with the transmit driver =
circuitry and the> > ESD structures around it, the chip+package return lo=
ss> > degrades significantly and violates the 10dB spec.> >> > I was hopi=
ng to design an inductor on package to> > compensate for this cap and to =
bring the odd-mode Z to> > 50Ohms but in the TDR profile, the impedance> =
> discontinuity created by the chip C and the package> > impedance discon=
tinuity occur at different times. So> > regardless of what structural opt=
imization I do> > on-package, it does not i
> mprove the overall> > chip+package RL performance.> >> > Can anybody s=
hed some light on this or point me to> > some resources I can use.> >> > =
Regards,> >> > Jitesh Shah> > Advanced Package Design> > IDT> >> >> >> >>=
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