Hi Everybody, I am designing a flip chip package for multi-Gbps SerDes (6.25Gbps & above) where as a stand alone package, I am able to optimize the flip-chip interconnect structure to meet the return loss specification of 10dB for up to 2x the fundamental switching frequency i.e., 10GHz. But due to the on-chip parasitic capacitance (~800fF) associated with the transmit driver circuitry and the ESD structures around it, the chip+package return loss degrades significantly and violates the 10dB spec. I was hoping to design an inductor on package to compensate for this cap and to bring the odd-mode Z to 50Ohms but in the TDR profile, the impedance discontinuity created by the chip C and the package impedance discontinuity occur at different times. So regardless of what structural optimization I do on-package, it does not improve the overall chip+package RL performance. Can anybody shed some light on this or point me to some resources I can use. Regards, Jitesh Shah Advanced Package Design IDT ____________________________________________________________________________________ Be a better sports nut! Let your teams follow you with Yahoo Mobile. Try it now. http://mobile.yahoo.com/sports;_ylt=At9_qDKvtAbMuh1G1SQtBI7ntAcJ ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu