[SI-LIST] On-Chip Parasitic C & its effect on RL

Hi Everybody,

I am designing a flip chip package for multi-Gbps
SerDes (6.25Gbps & above) where as a stand alone
package, I am able to optimize the flip-chip
interconnect structure to meet the return loss
specification of 10dB for up to 2x the fundamental
switching frequency i.e., 10GHz. 

But due to the on-chip parasitic capacitance (~800fF)
associated with the transmit driver circuitry and the
ESD structures around it, the chip+package return loss
degrades significantly and violates the 10dB spec.

I was hoping to design an inductor on package to
compensate for this cap and to bring the odd-mode Z to
50Ohms but in the TDR profile, the impedance
discontinuity created by the chip C and the package
impedance discontinuity occur at different times. So
regardless of what structural optimization I do
on-package, it does not improve the overall
chip+package RL performance.

Can anybody shed some light on this or point me to
some resources I can use.

Regards,

Jitesh Shah
Advanced Package Design
IDT




      
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