[SI-LIST] Re: On-Chip Parasitic C & its effect on R

Dave,
 
Will a varistor (shunt), inductor (series) help for this case?  I don't have 
any simulator to try. Thanks.
 
Regards,
Celine > Date: Thu, 15 Nov 2007 20:03:42 -0700> From: telegrapher9@xxxxxxxxx> 
To: jeetshah@xxxxxxxxx> Subject: [SI-LIST] Re: On-Chip Parasitic C & its effect 
on R> CC: si-list@xxxxxxxxxxxxx> > Jitesh,> > does your chip have ODT? I ran a 
frequency domain sim using an> electronic Smith Chart and adding an inductor 
didn't help. I'm able to> rapidly sweep various component values and did not 
obtain good return> loss until adding some series resistance. Of course to keep 
the delay> low and not attentuate the signal too much this value I limited to 
25> ohms. Here is the model:> > 12 ps, 50 ohm t-line. 50 ohm ODT shunt. 25 ohms 
series resistor. 400> fF shunt, 5 ohm series, 400 fF shunt.> > This was modeled 
single-ended. Your application is differential, is> it? Also, the 25 ohm series 
resistor isolates the ESD circuitry. Not> good but this might lead to some more 
insight into this matching> problem. The ESD circuitry and driver/receiver are 
modeled as the 400> fF, 5 ohm, 400 fF.> > Dave Cuthbert> Consultant> > > On Nov 
15, 2007 5:48 PM, Jitesh Shah <jeetshah@xxxxxxxxx> wrote:> > Hi Everybody,> >> 
> I am designing a flip chip package for multi-Gbps> > SerDes (6.25Gbps & 
above) where as a stand alone> > package, I am able to optimize the flip-chip> 
> interconnect structure to meet the return loss> > specification of 10dB for 
up to 2x the fundamental> > switching frequency i.e., 10GHz.> >> > But due to 
the on-chip parasitic capacitance (~800fF)> > associated with the transmit 
driver circuitry and the> > ESD structures around it, the chip+package return 
loss> > degrades significantly and violates the 10dB spec.> >> > I was hoping 
to design an inductor on package to> > compensate for this cap and to bring the 
odd-mode Z to> > 50Ohms but in the TDR profile, the impedance> > discontinuity 
created by the chip C and the package> > impedance discontinuity occur at 
different times. So> > regardless of what structural optimization I do> > 
on-package, it does not improve the overall> > chip+package RL performance.> >> 
> Can anybody shed some light on this or point me to> > some resources I can 
use.> >> > Regards,> >> > Jitesh Shah> > Advanced Package Design> > IDT> >> >> 
>> >> > 
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