[SI-LIST] Re: Initial Delays in V-t Rise/Fall Curves in IBIS

Hi Arpad,

Thank you so much for your reply, it did clear my doubts well. 

Pugazh

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Muranyi, Arpad
Sent: Friday, October 22, 2010 7:30 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Initial Delays in V-t Rise/Fall Curves in IBIS 

Pugazh,

The initial delays in V-t curves represent the delay across the buffer
from the time the stimulus switches to the time when the output changes.
This delay is not very useful because it all depends on how many of
the pre-driver circuitry is included in the transistor model from which
you are extracting the V-t curves.  We usually don't use this delay in
SI simulations, because flight times are usually calculated from a
waveform which is driven by a buffer loaded with the test load that is
used for the Tco specification of the buffer.

You can safely remove this delay time from the V-t tables, but be
careful
to remove the same absolute amount from all of the tables.  You cannot
remove different amounts because that will upset the on/off switching
relationships of the pullup and pulldown structures.

To answer why these delays are there in the IBIS models, I have to say
that it depends.  There are times when the model makers are forced to
remove these delays because otherwise the transition would not fit into
the bit time window and the IBIS model would become over-clocked.
When this is not a problem, it is simply a matter of choice to leave
these delays in the V-t tables.  It is easier not have to remove the
delay, so by default people would naturally leave it that way.

Removing this delay will not have an effect on Setup and Hold timings
at all (if those measurements are done correctly).

The delays do not "have to be" removed normally, only if the transition
time (edge rate) of the buffer is relatively slow with respect to the
bit time which would cause the model to be over clocked at its normal
operating frequency.

I hope this helps your understanding of the problem.

Arpad
========================================================================
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Pugazharasan Selvanathan - ERS, HCL Tech
Sent: Friday, October 22, 2010 8:32 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Initial Delays in V-t Rise/Fall Curves in IBIS 

Hi all,
Am doing timing analysis for DDR3 interface with Hyperlynx. I need to
validate the DDR3 controller and DRAM IBIS models before using them in
simulations. Both the models have some amount of initial time delays in
their V-t curves. I understand that this initial non-switching time
should be removed from the IBIS models before using them in timing
analysis for source synchronous interfaces like DDR3.

Have a few questions now...


1.       How much will be impact of this "removing initial delays" on
the setup and hold time margins?

2.       If the initial non-switching delay be removed, why it should be
specified in the IBIS model first? Excluding the relative delay between
different V-t tables.

3.       If the initial delays has to be removed, what should be the %
Voltage Threshold I should use?

Also, are there any standard timing specification for DDR3 Controller?
We are yet to receive that from the ASIC vendor, but wanted to go with
default timing spec. Right now we are in the process of delay matching
the addr./Clock/DQ/DQS group. So this information will of much help.

For strict timing analysis, should I have to include the package delays
also (Delay from die to pin) of DDR3 compliant DRAM in the timing margin
calculations?

Regards,
Pugazh


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