[SI-LIST] Initial Delays in V-t Rise/Fall Curves in IBIS
- From: "Pugazharasan Selvanathan - ERS, HCL Tech" <pugazharasan.s@xxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 22 Oct 2010 19:02:05 +0530
Hi all,
Am doing timing analysis for DDR3 interface with Hyperlynx. I need to validate
the DDR3 controller and DRAM IBIS models before using them in simulations. Both
the models have some amount of initial time delays in their V-t curves. I
understand that this initial non-switching time should be removed from the IBIS
models before using them in timing analysis for source synchronous interfaces
like DDR3.
Have a few questions now...
1. How much will be impact of this "removing initial delays" on the setup
and hold time margins?
2. If the initial non-switching delay be removed, why it should be
specified in the IBIS model first? Excluding the relative delay between
different V-t tables.
3. If the initial delays has to be removed, what should be the % Voltage
Threshold I should use?
Also, are there any standard timing specification for DDR3 Controller? We are
yet to receive that from the ASIC vendor, but wanted to go with default timing
spec. Right now we are in the process of delay matching the addr./Clock/DQ/DQS
group. So this information will of much help.
For strict timing analysis, should I have to include the package delays also
(Delay from die to pin) of DDR3 compliant DRAM in the timing margin
calculations?
Regards,
Pugazh
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