[SI-LIST] Re: How to simulate worse case eye
- From: "QU Perry" <Perry.Qu@xxxxxxxxxxxxxxxxxx>
- To: <al.neves@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 11 Mar 2009 09:31:45 -0500
Al:
I think we all agree that channel insertion loss and ISI induced by reflection
are the first order factor that affects serdes link performance, and that's why
so many tool vendors come up with some form of fast eye simulation engine,
e.g., starting from Cadence Channel designer, and Hyperlynx Fasteye, Ansoft
Designer, Quantum Channel Designer, ADS, Sigrity, etc. Mode conversion,
crosstalk together with the performance of active devices are important and I
agree that we need to do our due diligence on that.
And I don't plan on running long PRBS pattern simulation on all my test cases
as it's not possible due to run time and solution space. However, I do want to
have some confidence on the fast eye algorithm and understand its limitations
before I blindly apply them on all the designs.
I'm curious to learn your methodology of designing serdes, e.g., if you were
given a measured channel model with crosstalk included and you were asked the
question "can you run 5Gbps on that channel using XYZ chip on Tx and ABC chip
on Rx". What will you do? We were asked such questions a lot except we have to
come up with a valid passive channel model ourselves. Usually such channel is
not very well behaved e.g. we want to run faster on legacy system or constraint
by cost.
Regards
Perry
=======================================
Perry Qu
IPD Design & Qualification, Alcatel-Lucent Canada Inc.
600 March Road, Ottawa ON, K2K 2E6, Canada
DID: 613-7846720 Fax: 613-5993642
Email: perry.qu@xxxxxxxxxxxxxxxxxx
=======================================
-----Original Message-----
From: Alfred P. Neves [mailto:al.neves@xxxxxxxxxxx]
Sent: Tuesday, March 10, 2009 8:57 PM
To: QU Perry; 'Dmitriev-Zdorov, Vladimir'; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: How to simulate worse case eye
Am I missing something here? If I examine a full S-parameter description of
a LTI passive channel that is relatively behaved, such that there are no
deep resonances within the first or second spectral null frequency of the
input TX power spectral density, my experience suggests that ISI impacts
between n-bits of data is relatively constrained to a reasonable length. In
fact I believe this is shown by expanding the impulse response of the
channel into a Taylor series such that the higher order terms generally drop
off rapidly suggesting there is a reasonable constraint. In other words,
higher order derivatives (such as deep VIA or cavity type resonances) relate
to a longer interaction ISI length.
Worse eye pathology, in my experience, is dramatically impacted by the noise
injected into PLL-VCO substrates, crosstalk from long length PRBS
aggressors, supply resonance, RJ due to PLL VCO, SSO, SSN, RJ due to input
referred noise to the RX, variations of PLL loop dynamics to long 111's or
0000's, etc.,. Adding silicon changes the picture in other words.
Is running gazzilions of bits for passive LTI channels (no Pll's or RJ in
other words) a solution looking for a problem? My thinking is that be
evaluating the channel's signal integrity (including mode conversion,
crosstalk as measured with S-parameters, impedance variation, etc,) you will
learn a lot more than running LOTS of bits in the time domain.
It would be interesting to chart (simulated and measured) peak-peak DJ
versus simulation run length in #bits for a host of channel models ranging
from very well behaved to very poor S.I. and maybe highly resonant, also
including a channel model with 1-7% PRBS crosstalk with varying length (2^7
to 2^31).
Alfred P. Neves `·.¸¸.·´¯`·.. ><((((º>
.¸¸.·´¯`·.¸><((((º>`·.¸¸.·´¯`·.. ><((((º>
735 South East 16th Avenue
Hillsboro, OR 97123
(503) 718 7172 Office
(503) 679 2429 Mobile
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of QU Perry
Sent: Tuesday, March 10, 2009 1:28 PM
To: Dmitriev-Zdorov, Vladimir; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: How to simulate worse case eye
Hi, Vladmir:
Thanks for the pointer. I will take a look of the training video. Will
also check what's new on HL 8.0. Currently we are running 7.7 but we
plan to try the 8.0 Beta.
Agree that running long PRBS pattern in Hspice or any time domain solver
is very time consuming, but as a minimum I hope that I can verify the
fasteye algorithm to certain extent by doing some comparisons on
selected case with old/plain Hspice simulation and get some confidence
on the results.
On a side note, I wish we can separate Hspice with Hyperlynx as my
limited experience of running Hspice within HL is not very positive.
Another issue is encrypted I/O model and it's not very straightforward
to run Hspice sim within HL using encrypted models. Will I be able to
run a pulse/step response outside of HL and just bring in a voltage/time
waveform into HL for fast eye calculation? That would be ideal for me.
We can talk more offline or if you have a support person that I should
speak to, please let me know.
Regards
Perry
=======================================
Perry Qu
IPD Design & Qualification, Alcatel-Lucent Canada Inc.
600 March Road, Ottawa ON, K2K 2E6, Canada
DID: 613-7846720 Fax: 613-5993642
Email: perry.qu@xxxxxxxxxxxxxxxxxx
=======================================
-----Original Message-----
From: Dmitriev-Zdorov, Vladimir
[mailto:vladimir_dmitriev-zdorov@xxxxxxxxxx]
Sent: Tuesday, March 10, 2009 1:27 PM
To: QU Perry; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: How to simulate worse case eye
Hi Perry,
In fact, you may choose between at least 3 different simulators when
running for step or impulse response in Hyperlynx (including HSPICE;
they are integrated). The result of this test simulation is fed directly
to FastEye engine that is a part of Hyperlynx and performs fast time
domain, worst case and statistical analysis for eye diagram/BER etc.
>I was thinking about feeding a PRBS31 pattern into a 8b/10B encoder and
use >the output of encoder as input excitation in simulation.
Yes, this is a good idea. In "fast" time domain analysis, we support
pseudo random generation of the 8b/10b pattern, but we do not base this
generation on any cyclic source, like LFSR, to avoid periodicity. This
way we may get any combination that does fit into 8b/10b constrains.
However, even though 8b/10b is a subclass of general unconstrained
pattern, it still has sufficient "variability" preventing us from
finding the worst case by simply performing long simulation. For
example, some time ago, we performed an experiment where such non-cyclic
"pseudo random" 8b10b pattern was running on 1 trillion = 1e12 bits
(took about 3 weeks to complete). Still, the resulting eye contour was
unable to approach to a 100 bit long worst 8b10b combination that can be
found from the worst case analysis in a fraction of a second. The eye
height that the worst pattern provided was about 12% smaller than we get
from this long simulation.
My guess is that PRBS7 is often used as a substitute for 8b10b, because
it has approximately same running length. However, it still may have 7
ones in a row, and in a long run, it does not support disparity between
its 4/6 bit words, and globally: with 127 bit period, it simply cannot
contain equal number of ones and zeros.
Vladimir
There is a tutorial video showing how you use HyperLynx FastEye in v7.7
which is the tool that generates the worst case bit sequence.
http://supportnet.mentor.com/reference/tutorials/50024.cfm
There is also a possibility to get the license and try the new beta
version that is more flexible in terms of providing channel
characterization.
-----Original Message-----
From: QU Perry [mailto:Perry.Qu@xxxxxxxxxxxxxxxxxx]
Sent: Tuesday, March 10, 2009 10:32 AM
To: Dmitriev-Zdorov, Vladimir; si-list@xxxxxxxxxxxxx
Cc: Oh, Dan
Subject: RE: [SI-LIST] Re: How to simulate worse case eye
Hi, Vladimir:
Would you be able to provide some more details on the simulation flow
you mentioned using Hyperlynx? If I understand correctly, you extract
step response or pulse response separately in Hspice and then feed that
waveform into HL for worst case eye simulation ? Do we need the new
version of HL for that (8.0)?
I also share your observation on using long PRBS pattern on AC coupled
serdes channel can be over-pessimistic for 8b/10b encoded system from DC
balance point of view. PRBS7 on the other hand does provide enough
pattern variation and can be too optimistic. I was thinking about
feeding a PRBS31 pattern into a 8b/10B encoder and use the output of
encoder as input excitation in simulation. We asked Synopsys to add
8b/10b encoder in LSFR function and they agreed to do that.
Dan: I'm interested in your paper. Can you please send me a copy?
Thanks!
Perry
=======================================
Perry Qu
IPD Design & Qualification, Alcatel-Lucent Canada Inc.
600 March Road, Ottawa ON, K2K 2E6, Canada
DID: 613-7846720 Fax: 613-5993642
Email: perry.qu@xxxxxxxxxxxxxxxxxx
=======================================
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Dmitriev-Zdorov, Vladimir
Sent: Saturday, March 07, 2009 10:02 AM
To: Dmitriev-Zdorov, Vladimir; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: How to simulate worse case eye
Tim/Joel,
Perhaps, I should have given more details in my previous reply.
Yes, the paper of Brian Casper, and even some earlier works give us a
method of building an unconstrained worst case pattern; that is
relatively simple. I would also recommend reading this paper as an
excellent introduction into the topic.
However, this approach does not answer all practical needs, including
the following.
1. Encoded worst case pattern. In many important cases the
unconstrained worst case solution does not have much value. If e.g. the
SERDES channel includes series capacitor(s), we know that the eye will
be closed by sufficiently long series of logical 'ones' or 'zeros'. The
longer is a series of identical bits, the more closed the eye becomes.
In this sense, there is no 'worst' unconstrained solution, unless the
pattern length is limited. Of course, in such channels only encoded
binary inputs are allowed (8b10b or some others), with their imparity
and running length constraints, for which the idea of 'worst case
pattern' makes a perfect sense. There exists a solution for such case in
HL.
2. Some types of non-LTI behavior. For example, in many cases the
responses to rising and falling transitions are not symmetrical, that
means their sum R(t) + F(t) is not identical constant. There are several
sources of this phenomenon: (a) persistent time shift between R/F
transitions (DCD), (b) asymmetry of PU and PD I-V or timing
characteristics in a single ended channel, or (c) partial conversion of
near end common signal into far end differential signal, that may occur
even with identical differential buffers, if linear part of the channel
is not ideally symmetric (creates differential skew).
In the recent Mentor/Tek paper "New methods of measuring the performance
of equalized serial data links and correlation of performance measures
across the design flow..." from DesignCon2009 we considered worst case
solutions, including cases (1), (2) and combination of (1) and (2).
>
>
>
>
Joel,
I'm sure there will be no shortage of recommendations here, but here's
my contribution:
It's pretty easy to determine the worst case pattern for a single route,
assuming the system is linear-time-invariant.
1. Start by generating the pulse response of the system.
2. Then sample the response at UI intervals from the Peak or cursor
sample, or just eyeball the ISI at these intervals.
3. Based on the direction or polarity of the ISI terms, and their
relative distances from the cursor (in UI), you can determine what input
pattern can be used to maximize the combined contributions of the ISI
terms. Positive-going ISI terms eat away from the nominal zero level,
and negative-going ISI terms eat away from the nominal one level.
4. You can then move your cursor away from the peak of the pulse
response and repeat the process to determine patterns targeting points
across the width of the eye if desired.
If you haven't read it, check out Bryan Casper's paper describing the
use of Peak Distortion analysis to generate Worst Case Eyes. It doesn't
explicitly tell you how to generate the worst case pattern, but it may
inspire you.
B.K. Casper, et al, "An accurate and efficient analysis method for
multi-Gb/s chip-to-chip signaling schemes."
If you've got IEEE access:
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber15043&isnumber!8
31
Tim Hollis
DRAM Design
Micron Technology, Inc.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Joel Brown
Sent: Friday, March 06, 2009 3:35 PM
To: SI-LIST@xxxxxxxxxxxxx
Subject: [SI-LIST] How to simulate worse case eye
I was watching a webinar by Mentor on Hyperlynx and how they can quickly
generate a prbs pattern that results in a worse case eye diagram. They
said
without this feature it could take days or even years of simulation to
do
this.
I do most of my simulation in hspice since most of my models are based
in
Hspice.
Is there a way to do what Mentor is claiming in Hspice by generating a
certain pattern?
I have been using the following code for a prbs sequence:
vin inr vcm LFSR(0.1 -0.1 1n 5ps 5ps
+ 'data_rate' 1 [7,4,1] rout=0)
vinn innr vcm LFSR(-0.1 0.1 1n 5ps 5ps
+ 'data_rate' 1 [7,4,1] rout=0)
Thanks - Joel
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