Posts for si-list, 03-2009

Browse: Last Month: 02-2009 Main Archive Page Next Month: 04-2009

» [SI-LIST] Straw poll: Which phrase best describes your usage of IBIS AMI? - colin_warwick
» [SI-LIST] Re: Question about the usage of package model(.pkg) in IBIS and the [Package] parameter - Ray Anderson
» [SI-LIST] Question about the usage of package model(.pkg) in IBIS and the [Package] parameter - Seshadri Venkataramanan
» [SI-LIST] 姚潔茹感覺他的陰莖好粗把自己久曠的陰道撐得滿滿的 - f83118
» [SI-LIST] Re: timing analysis - Istvan Nagy
» [SI-LIST] Re: timing analysis - Mike Williams
» [SI-LIST] Who wants 5 minutes of fame? - eric bogatin
» [SI-LIST] Re: timing analysis - Hal Murray
» [SI-LIST] Re: A question about Rocketio hspice model - Ray Anderson
» [SI-LIST] Re: timing analysis - Lee Ritchey
» [SI-LIST] A question about Rocketio hspice model - fangod
» [SI-LIST] Re: small signal AC model for Current mode DC_DC converters, for full PDN simulation - Istvan Nagy
» [SI-LIST] Re: RF Shiled - Todd Hubing
» [SI-LIST] Re: small signal AC model for Current mode DC_DC converters, for full PDN simulation - earl albin
» [SI-LIST] RF Shiled - sunil bharadwaz
» [SI-LIST] Re: small signal AC model for Current mode DC_DC converters, for full PDN simulation - earl albin
» [SI-LIST] Re: John De Falco paper on crosstalk - Brian Schieck
» [SI-LIST] Re: John De Falco paper on crosstalk - David Oka
» [SI-LIST] Re: timing analysis - Todd Westerhoff
» [SI-LIST] Re: timing analysis - Bradley Henson
» [SI-LIST] Re: timing analysis - Peterson, James F (EHCOE)
» [SI-LIST] Re: About Hspice warning - Tracy Barclay
» [SI-LIST] Re: small signal AC model for Current mode DC_DC converters, for full PDN simulation - Allen Mayar/EXTON/USA/SALES/KEMET/US
» [SI-LIST] timing analysis - Gregory R Edlund
» [SI-LIST] Re: timing analysis - Haller, Robert
» [SI-LIST] Re: PI Analysis doubts (please help) - Plane pair problem - Istvan Novak
» [SI-LIST] Re: timing analysis - Robert Szumowicz
» [SI-LIST] Re: PS/2 Mouse Interface protocol - liuluping 41830
» [SI-LIST] Re: small signal AC model for Current mode DC_DC converters, for full PDN simulation - steve weir
» [SI-LIST] small signal AC model for Current mode DC_DC converters, for full PDN simulation - Istvan Nagy
» [SI-LIST] About Hspice warning - fangod
» [SI-LIST] Re: Loop inductance of regulator - steve weir
» [SI-LIST] Loop inductance of regulator - Lakshmi Narayanan Sowrirajan, TLS-Chennai
» [SI-LIST] Re: PI Analysis doubts (please help) - Plane pair problem - steve weir
» [SI-LIST] PI Analysis doubts (please help) - Plane pair problem - Lakshmi Narayanan Sowrirajan, TLS-Chennai
» [SI-LIST] Re: timing analysis - Istvan Nagy
» [SI-LIST] Re: timing analysis - wolfgang . maichen
» [SI-LIST] timing analysis - Harwood, Morton (GE Infra, Aviation, US)
» [SI-LIST] PS/2 Mouse Interface protocol - chao wang
» [SI-LIST] PI Analysis doubts (please help) - Plane pair problem - Lakshmi Narayanan Sowrirajan, TLS-Chennai
» [SI-LIST] PI Analysis doubts (please help) - Plane pair problem - Lakshmi Narayanan Sowrirajan, TLS-Chennai
» [SI-LIST] FW: PI Analysis doubts (please help) - Plane pair problem - Lakshmi Narayanan Sowrirajan, TLS-Chennai
» [SI-LIST] Re: Signal Integrity for PCB Designers - V S
» [SI-LIST] Signal Integrity for PCB Designers - V S
» [SI-LIST] USB 3.0 questions - J. Eric Gamble
» [SI-LIST] USB 3.0 questions - J. Eric Gamble
» [SI-LIST] Re: homework - Muranyi, Arpad
» [SI-LIST] Re: homework - Jack Olson
» [SI-LIST] Re: command line impedance calculator - Istvan Nagy
» [SI-LIST] Re: command line impedance calculator - Doug Brooks
» [SI-LIST] Re: homework - Doug Brooks
» [SI-LIST] Re: command line impedance calculator - wolfgang . maichen
» [SI-LIST] Re: homework - Jack Olson
» [SI-LIST] homework - Gregory R Edlund
» [SI-LIST] Re: command line impedance calculator - Sanjeev Gupta
» [SI-LIST] command line impedance calculator - Sanjeev Gupta
» [SI-LIST] Re: Transmission Line calculator Problem!--> use my stripline calculator - its Free - Salkow, Steven
» [SI-LIST] Re: S-parameter file viewing tool - Smith, David
» [SI-LIST] Re: S-parameter file viewing tool - Scott McMorrow
» [SI-LIST] [RESEND] European IBIS Summit @ DATe 2009 - Third Call for Participation - Ralf Brüning
» [SI-LIST] S-parameter file viewing tool - Peter . Pupalaikis
» [SI-LIST] Re: homework - salammon@xxxxxxxx
» [SI-LIST] Re: Tutorial needed - fpz
» [SI-LIST] Re: High-Speed (coax) PCB Connector Transitions -- selection, PCB footprint, and performance - wolfgang . maichen
» [SI-LIST] Re: homework - Doug Brooks
» [SI-LIST] homework - salammon@xxxxxxxx
» [SI-LIST] Re: Tutorial needed - Gene Garat
» [SI-LIST] Tutorial needed - Mohamad Haghtalab
» [SI-LIST] Re: PCB layout simulation test plan - Scott McMorrow
» [SI-LIST] Re: How to simulate worse case eye - Todd Westerhoff
» [SI-LIST] PCB layout simulation test plan - Sankar K
» [SI-LIST] Re: Transmission Line calculator Problem! - V S
» [SI-LIST] European IBIS Summit @ DATe 2009 - Third Call for Participation - Ralf Brüning
» [SI-LIST] Re: Transmission Line calculator Problem! - Mikhail Matusov
» [SI-LIST] Re: Transmission Line calculator Problem! - Nash, Timothy J
» [SI-LIST] Re: Transmission Line calculator Problem! - Lee Ritchey
» [SI-LIST] Re: Transmission Line calculator Problem! - Mikhail Matusov
» [SI-LIST] Transmission Line calculator Problem! - Mohamad Haghtalab
» [SI-LIST] Re: V-level of LVDS jitter measurement - Richard Jungert
» [SI-LIST] Re: V-level of LVDS jitter measurement - Jory McKinley
» [SI-LIST] Re: AW: Patch Antenna Design for UHF RFID reader - Vinod Kumar
» [SI-LIST] hi - navaram kumar
» [SI-LIST] Re: rush of current at power on - Aravind Sandeep
» [SI-LIST] V-level of LVDS jitter measurement - Peterson, James F (EHCOE)
» [SI-LIST] rush of current at power on - sunil bharadwaz
» [SI-LIST] AW: Patch Antenna Design for UHF RFID reader - Havermann, Gert
» [SI-LIST] Re: Potentially Dumb Question About Routing Layers - DAVID CUTHBERT
» [SI-LIST] Patch Antenna Design for UHF RFID reader - Vinod Kumar
» [SI-LIST] Transceiver Design Workshop with Dr. Eric Bogatin - April 2, 2009 - Salman Jiva
» [SI-LIST] Re: AW: What is 'Integrated RMS jitter' and how is it measured - Bharathi
» [SI-LIST] Re: How to simulate worse case eye - QU Perry
» [SI-LIST] Re: How to simulate worse case eye - Dmitriev-Zdorov, Vladimir
» [SI-LIST] Re: Potentially Dumb Question About Routing Layers - Arnold, Peter
» [SI-LIST] Potentially Dumb Question About Routing Layers - Nash, Timothy J
» [SI-LIST] Re: layer stackup assignment - olaney
» [SI-LIST] Re: How to simulate worse case eye - Alfred P. Neves
» [SI-LIST] layer stackup assignment - Jie Wang
» [SI-LIST] Re: How to simulate worse case eye - Scott McMorrow
» [SI-LIST] Re: What is 'Integrated RMS jitter' and how is it measured - robert_sleigh
» [SI-LIST] Re: How to simulate worse case eye - Dmitriev-Zdorov, Vladimir
» [SI-LIST] Re: Switching power supply Vs. Linear power supply for Processor Core and IO - earl albin
» [SI-LIST] Re: How to simulate worse case eye - QU Perry
» [SI-LIST] Re: What is 'Integrated RMS jitter' and how is it measured - K K
» [SI-LIST] Re: What is 'Integrated RMS jitter' and how is it measured - marcus_mueller2
» [SI-LIST] AW: What is 'Integrated RMS jitter' and how is it measured - Havermann, Gert
» [SI-LIST] What is 'Integrated RMS jitter' and how is it measured - Henrik G Madsen
» [SI-LIST] Re: Impedance match of a 100Mhz line - Andrew Ingraham
» [SI-LIST] Re: How to simulate worse case eye - Alfred P. Neves
» [SI-LIST] Re: How to simulate worse case eye - Kaufer, Steve
» [SI-LIST] Re: How to simulate worse case eye - QU Perry
» [SI-LIST] Re: Timing analysis between PXA270 and CPLD - Istvan Nagy
» [SI-LIST] Re: How to simulate worse case eye - Dmitriev-Zdorov, Vladimir
» [SI-LIST] Re: High-Speed (coax) PCB Connector Transitions -- selection, PCB footprint, and performance - QU Perry
» [SI-LIST] Re: How to simulate worse case eye - QU Perry
» [SI-LIST] Re: High-Speed (coax) PCB Connector Transitions -- selection, PCB footprint, and performance - Scott McMorrow
» [SI-LIST] Timing analysis between PXA270 and CPLD - Vivekkumar M-TLS,Chennai
» [SI-LIST] AW: High-Speed (coax) PCB Connector Transitions -- selection, PCB footprint, and performance - Havermann, Gert
» [SI-LIST] Re: Impedance match of a 100Mhz line - Bharathi
» [SI-LIST] Re: Switching power supply Vs. Linear power supply for Processor Core and IO - Bharathi
» [SI-LIST] Re: High-Speed (coax) PCB Connector Transitions -- selection, PCB footprint, and performance - Barnes, Heidi
» [SI-LIST] Re: High-Speed (coax) PCB Connector Transitions -- selection, PCB footprint, and performance - wolfgang . maichen
» [SI-LIST] Re: Switching power supply Vs. Linear power supply for Processor Core and IO - steve weir
» [SI-LIST] Switching power supply Vs. Linear power supply for Processor Core and IO - V S
» [SI-LIST] Re: High-Speed (coax) PCB Connector Transitions -- selection, PCB footprint, and performance - Barnes, Heidi
» [SI-LIST] Re: How to simulate worse case eye - Dmitriev-Zdorov, Vladimir
» [SI-LIST] High-Speed (coax) PCB Connector Transitions -- selection, PCB footprint, and performance - Michael Rodrigues
» [SI-LIST] Re: How to simulate worse case eye - Vinu Arumugham
» [SI-LIST] Re: How to simulate worse case eye - Oh, Dan
» [SI-LIST] Re: How to simulate worse case eye - Dmitriev-Zdorov, Vladimir
» [SI-LIST] FW: Center Resonance Frequency in calculating the Q of System - Lakshmi Narayanan Sowrirajan, TLS-Chennai
» [SI-LIST] Re: Impedance match of a 100Mhz line - Andrew Ingraham
» [SI-LIST] Re: How to simulate worse case eye - thollis
» [SI-LIST] Impedance match of a 100Mhz line - Barthi das
» [SI-LIST] Center Resonance Frequency in calculating the Q of System - Lakshmi Narayanan Sowrirajan, TLS-Chennai
» [SI-LIST] Re: How to simulate worse case eye - Dmitriev-Zdorov, Vladimir
» [SI-LIST] SI Engineer/Sr SI Engineer position is available at Adaptec, Inc - Mangipudi, Prasad
» [SI-LIST] Re: How to simulate worse case eye - Scott McMorrow
» [SI-LIST] How to simulate worse case eye - Dmitriev-Zdorov, Vladimir
» [SI-LIST] Re: How to simulate worse case eye - thollis
» [SI-LIST] How to simulate worse case eye - Joel Brown
» [SI-LIST] Re: Xilinx SpartanT-3/3E/3L FPGA Power Solutions-- FromMonolithic Solutions - steve weir
» [SI-LIST] Re: general belief about Xtalk - Lee Ritchey
» [SI-LIST] Re: general belief about Xtalk - Mick zhou
» [SI-LIST] Re: question about voltage dividers - steve weir
» [SI-LIST] Re: Xilinx SpartanT-3/3E/3L FPGA Power Solutions-- FromMonolithic Solutions - Bharathi
» [SI-LIST] Re: question about voltage dividers - DAVID CUTHBERT
» [SI-LIST] Re: footprint for 100-pin Hirose FX2 socket connector - Harry Selfridge
» [SI-LIST] FW: Re: question about voltage dividers - Richard Jungert
» [SI-LIST] Re: Xilinx SpartanT-3/3E/3L FPGA Power Solutions-- FromMonolithic Solutions - istvan Novak
» [SI-LIST] Packaging Opportunity at AMCC/Either in Sunnyvale or San Diego - Dev Malladi
» [SI-LIST] Senior Signal Integrity opening with Juniper Networks (Sunnyvale, CA) - Luong
» [SI-LIST] Re: question about voltage dividers - wolfgang . maichen
» [SI-LIST] Re: question about voltage dividers - Doug Brooks
» [SI-LIST] Re: general belief about Xtalk - Howard Johnson
» [SI-LIST] Re: question about voltage dividers - wolfgang . maichen
» [SI-LIST] Re: question about voltage dividers - Doug Brooks
» [SI-LIST] Re: question about voltage dividers - Tom Dagostino
» [SI-LIST] Re: Xilinx SpartanT-3/3E/3L FPGA Power Solutions-- FromMonolithic Solutions - Harry Lin
» [SI-LIST] Re: question about voltage dividers - Andrew Ingraham
» [SI-LIST] Re: question about voltage dividers - DAVID CUTHBERT
» [SI-LIST] footprint for 100-pin Hirose FX2 socket connector - chao wang
» [SI-LIST] Re: Xilinx SpartanT-3/3E/3L FPGA Power Solutions-- FromMonolithic Solutions - Vivekkumar M-TLS,Chennai
» [SI-LIST] Re: Xilinx SpartanT-3/3E/3L FPGA Power Solutions-- From Monolithic Solutions - Siddesh V
» [SI-LIST] Re: Xilinx SpartanT-3/3E/3L FPGA Power Solutions-- From Monolithic Solutions - istvan Novak
» [SI-LIST] Xilinx SpartanT-3/3E/3L FPGA Power Solutions-- From Monolithic Solutions - Vivekkumar M-TLS,Chennai
» [SI-LIST] AW: question about voltage dividers - Havermann, Gert
» [SI-LIST] Re: question about voltage dividers - Eugenio Simões
» [SI-LIST] Re: question about voltage dividers - Haller, Motti
» [SI-LIST] Re: question about voltage dividers - Roy M
» [SI-LIST] Re: question about voltage dividers - Pramod Parameswaran
» [SI-LIST] question about voltage dividers - Roy M
» [SI-LIST] March 2009 Technical Tidbit - Current Probes, More Useful Than You Think - Part 3 - Doug Smith
» [SI-LIST] Re: 180 degree turns in high speed lines - Duane Mattheisen
» [SI-LIST] Re: 180 degree turns in high speed lines - Eugenio Simões
» [SI-LIST] Central Pennsylvania's Third Symposium on Signal Integrity - Clewell, Craig
» [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias?? - Richard Jungert
» [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias?? - Stefan Milnor
» [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias?? - Jack Olson
» [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias?? - Richard Jungert
» [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias?? - Istvan Novak
» [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias?? - steve weir
» [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias?? - ManatoshGBaidya
» [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias?? - steve weir
» [SI-LIST] Advantages & Disadvantages of Flooding Vias?? - ManatoshGBaidya
» [SI-LIST] Re: final note on XTK - Istvan Novak
» [SI-LIST] final note on XTK - eric bogatin